National Semiconductor CP3BT26 User Manual page 244

Reprogrammable connectivity processor with bluetooth, usb, and can interfaces
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Symbol
I
Output Leakage Current
O(Off)
(I/O pins in input mode)
Icca1
Digital Supply Current Active Mode
Iccprog
Digital Supply Current Active Mode
Iccps
Digital Supply Current Power Save Mode
Iccid
Digital Supply Current Idle Mode
Iccq
Digital Supply Current Halt Mode
a. Guaranteed by design
b. Run from internal memory (RAM), Iout = 0 mA, X1CKI = 12 MHz, PLL enabled (4×), internal system clock is
24 MHz, not programming Flash memory
c. Same conditions as Icca1, but programming or erasing Flash memory page
d. Running from internal memory (RAM), Iout = 0 mA, XCKI1 = 12 MHz, PLL disabled, X2CKI = 32.768 kHz,
device put in power-save mode, Slow Clock derived from XCKI1
e. Iout = 0 mA, XCKI1 = Vcc, X2CKI = 32.768 kHz
f. Halt current approximately doubles for every 20°C.
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Parameter
b
c
d
e
e,f
Conditions
0V ≤ Vout ≤ Vcc
Vcc = 2.75V,
IOVcc=3.63V
Vcc = 2.75V,
IOVcc = 3.63V
Vcc = 2.75V,
IOVcc =3.63V
Vcc = 2.75V,
IOVcc = 3.63V
Vcc = 2.75V,
IOVcc = 3.63V,
20°C
244
Min
Max
-2.0
2.0
20
20
4
2
150
Units
µA
mA
mA
mA
mA
µA

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