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National Semiconductor CP3BT26 User Manual

Reprogrammable connectivity processor with bluetooth, usb, and can interfaces
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CP3BT26 Reprogrammable Connectivity Processor with
®
Bluetooth
, USB, and CAN Interfaces
1.0

General Description

The CP3BT26 connectivity processor combines high perfor-
mance with the massive integration needed for embedded
Bluetooth applications. A powerful RISC core with on-chip
SRAM and Flash memory provides high computing band-
width, hardware communications peripherals provide high-
I/O bandwidth, and an external bus provides system ex-
pandability.
On-chip communications peripherals include: Bluetooth
Lower Link Controller, Universal Serial Bus (USB) 1.1 node,
CAN, Microwire/Plus, SPI, ACCESS.bus, quad UART, 12-bit
A/D converter, and Advanced Audio Interface (AAI). Addi-
tional on-chip peripherals include Random Number Gener-
ator (RNG), DMA controller, CVSD/PCM conversion
module, Timing and Watchdog Unit, Versatile Timer Unit,
Multi-Function Timer, and Multi-Input Wake-Up (MIWU)
unit.
Bluetooth hand-held devices can be both smaller and lower
in cost for maximum consumer appeal. The low voltage and

Block Diagram

Clock Generator
12 MHz and 32 kHz
PLL and Clock
Oscillator
Generator
256K Bytes
CR16C
Flash
CPU Core
Program
Memory
Bus
DMA
Interface
Controller
Unit
Audio
GPIO
Interface
Bluetooth is a registered trademark of Bluetooth SIG, Inc. and is used under license by National Semiconductor.
TRI-STATE is a registered trademark of National Semiconductor Corporation.
©2004 National Semiconductor Corporation
Power-on-Reset
8K Bytes
32K Bytes
Flash
Static
Data
RAM
CPU Core Bus
Interrupt
Peripheral
Control
Bus
Unit
Controller
Peripheral Bus
ACCESS
Microwiire/
Quad UART
.bus
SPI
advanced power-saving modes achieve new design points
in the trade-off between battery size and operating time for
handheld and portable applications.
In addition to providing the features needed for the next gen-
eration of embedded Bluetooth products, the CP3BT26 is
backed up by the software resources designers need for
rapid time-to-market, including an operating system, Blue-
tooth protocol stack implementation, peripheral drivers, ref-
erence
designs,
environment. Combined with a Bluetooth radio transceiver
such as National's LMX5252, the CP3BT26 provides a com-
plete Bluetooth system solution.
National Semiconductor offers a complete and industry-
proven application development environment for CP3BT26
applications, including the IAR Embedded Workbench,
iSYSTEM winIDEA and iC3000 Active Emulator, Bluetooth
Development Board, Bluetooth Protocol Stack, and Applica-
tion Software.
Bluetooth Lower
Link Controller
RF Interface
Sequencer RAM
CAN 2.0B
Controller
Protocol
4.5K Bytes
Core
Power
CVSD/PCM
Manage-
Converter
ment
Versatile
Muti-Func-
Timer Unit
tion Timer
PRELIMINARY
and
an
integrated
development
1K Byte
Serial
Debug
Interface
Data RAM
Random
Timing and
Number
Watchdog
Generator
Unit
Multi-Input
8-Channel
USB
Wake-Up
12-bit ADC
www.national.com
MAY 2004
DS202

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Summary of Contents for National Semiconductor CP3BT26

  • Page 1: General Description

    Interface Timer Unit tion Timer Wake-Up 12-bit ADC DS202 Bluetooth is a registered trademark of Bluetooth SIG, Inc. and is used under license by National Semiconductor. TRI-STATE is a registered trademark of National Semiconductor Corporation. ©2004 National Semiconductor Corporation www.national.com...

  • Page 2: Table Of Contents

    Functional Description ....... . . 79 16.2 Touchscreen Interface ....... . . 81 www.national.com...

  • Page 3: Features

    -40° to +85°C LQFP-144 CP3BT26Y98NEPNOPB -40° to +85°C LQFP-144 CP3BT26Y98NEPX -40° to +85°C LQFP-144 CP3BT26Y98NEPXNOPB -40° to +85°C LQFP-144 NEP - Erased part (Bluetooth device address in Information Block 1); X - Tape and reel; NOPB - No lead solder www.national.com...

  • Page 4: Device Overview

    I/O. It determines the configured param- mer’s Reference Manual (document number 424521772- eters for bus access (such as the number of wait states for 101, which may be downloaded from National’s web site at memory access) and issues the appropriate bus signals for http://www.national.com).

  • Page 5: Bluetooth Llc

    Power Management Control Logic can share the same shift clock and frame sync signals for BlueRF-compatible interface (mode 2/3) to connect with synchronous mode operation. National’s LMX5252 and other RF transceiver chips 3.12 CVSD/PCM CONVERSION MODULE The CVSD/PCM module performs conversion between...

  • Page 6: Random Number Generator

    In addition, this module generates the device reset by using events. reset input signals coming from an external reset and vari- — Single Input Capture and Single Timer mode: Pro- ous on-chip modules. vides one external event counter and one system tim- www.national.com...

  • Page 7: Power Management

    CR16C (Software DMA request) iSYSTEM winIDEA and iC3000 Active Emulator, Bluetooth • Development Board, Bluetooth Protocol Stack, and Applica- • USART tion Software. See your National Semiconductor sales rep- • Advanced Audio Interface resentative for current information on availability and • CVSD/PCM Converter features of emulation equipment and evaluation boards.

  • Page 8: Signal Descriptions

    These pins may be individually con- figured as port pins, even when the associated peripheral or interface is enabled. Table 2 describes the device signals for the LQFP-128 package. Table 3 describes the device sig- nals for the LQFP-144 package. www.national.com...
  • Page 9 3.3V USB Transceiver Supply None None UVCC Input USB Transceiver Ground None None UGND ADC Input Channel 0 TSX+ Touchscreen X+ contact ADC0 ADC Input Channel 1 TSY+ Touchscreen Y+ contact ADC1 ADC Input Channel 2 TSX- Touchscreen X- contact ADC2 www.national.com...
  • Page 10 Versatile Timer Channel 8 Generic I/O RFSYNC BT AC Correlation/TX Enable Output Generic I/O RFCE BT RF Chip Enable Output BTSEQ1 Bluetooth Sequencer Status Generic I/O SRCLK AAI Receive Clock Generic I/O SCLK BT Serial I/F Shift Clock Output www.national.com...
  • Page 11 WUI21 Multi-Input Wake-Up Channel 21 Generic I/O WUI22 Multi-Input Wake-Up Channel 22 Generic I/O WUI23 Multi-Input Wake-Up Channel 23 Generic I/O WUI24 Multi-Input Wake-Up Channel 24 ASYNC Start convert signal to ADC Generic I/O WUI9 Multi-Input Wake-Up Channel 9 www.national.com...
  • Page 12 3.3V USB Transceiver Supply None None UVCC Input USB Transceiver Ground None None UGND ADC Input Channel 0 TSX+ Touchscreen X+ contact ADC0 ADC Input Channel 1 TSY+ Touchscreen Y+ contact ADC1 ADC Input Channel 2 TSX- Touchscreen X- contact ADC2 www.national.com...
  • Page 13 SPI Master Out Slave In Generic I/O TIO3 Versatile Timer Channel 3 MWCS SPI Slave Select Input Generic I/O TIO4 Versatile Timer Channel 4 AAI Clock Generic I/O TIO5 Versatile Timer Channel 5 AAI Frame Synchronization Generic I/O TIO6 Versatile Timer Channel 6 www.national.com...
  • Page 14 Multi-Input Wake-Up Channel 16 CANRX CAN Receive Input Generic I/O WUI17 Multi-Input Wake-Up Channel 17 Generic I/O CANTX CAN Transmit Output Generic I/O WUI18 Multi-Input Wake-Up Channel 18 ASYNC Start Convert Signal to ADC Generic I/O WUI9 Multi-Input Wake-Up Channel 9 www.national.com...

  • Page 15: Cpu Architecture

    16 bits. tecture, see the CompactRISC CR16C Programmer’s Ref- With the recommended calling convention for the architec- erence Manual which is available on the National ture, some of these registers are assigned special hardware Semiconductor web site (http://www.nsc.com).

  • Page 16: Processor Status Register (Psr)

    In a comparison of integers, the Z bit is set if the two operands are equal. If the oper- ands are unequal, the Z bit is cleared. – Source and destination operands un- equal. – Source and destination operands equal. www.national.com...

  • Page 17: Configuration Register (Cfg)

    RA register, and address displace- ments relative to a single register are supported with offsets of 0 and 14 bits in place of the index addressing with these displace- ments. – 32-bit registers are used. – 16-bit registers are used (CR16B mode). www.national.com...

  • Page 18: Addressing Modes

    CompactRISC CR16C Programmer's Reference Manual. In branch instructions, the displacement is always relative to the current value of the PC Register. For example, the follow- ing instruction causes an unconditional branch to an address 10 ahead of the current PC. BR *+10 www.national.com...

  • Page 19: Stacks

    RPlink Link register pair registers (such as the PSR). Rposition Bit position in register Rproc 16-bit processor register Rprocd 32-bit processor register RPsrc Source register pair RPtarget Target register pair Rsrc, Rsrc1, Rsrc2 Source register www.national.com...
  • Page 20 Logical OR: Rdest := RPdest | RPsrc/imm Scond Rdest Save condition code as boolean XORi Rsrc/imm, Rdest Logical exclusive OR: Rdest := Rdest ^ Rsrc/imm XORD RPsrc/imm, RPdest Logical exclusive OR: Rdest := RPdest ^ RPsrc/imm ASHUi Rsrc/imm, Rdest Arithmetic left/right shift www.national.com...
  • Page 21 Branch and link disp9 Branch disp17 disp24 EXCP vector Trap (vector) Jcond RPtarget Conditional Jump to a large address RA, RPtarget, Jump and link to a large address RPlink, RPtarget JUMP RPtarget Jump JUSR RPtarget Jump and set PSR.U www.national.com...
  • Page 22 Load 1 to 8 registers (R2-R5, R8-R11) from memory starting at (R0) LOADMP imm3 Load 1 to 8 registers (R2-R5, R8-R11) from memory starting at (R1, R0) STORM STORM imm3 Store 1 to 8 registers (R2-R5, R8-R11) to memory starting at (R2) www.national.com...
  • Page 23 Table 5 Instruction Set Summary Mnemonic Operands Description STORMP imm3 Store 1 to 8 registers (R2-R5, R8-R11) to memory starting at (R7,R6) Disable maskable interrupts Enable maskable interrupts EIWAIT Enable maskable interrupts and wait for interrupt No operation WAIT Wait for interrupt www.national.com...

  • Page 24: Memory

    EMPTY bits in the Protection word indicate that the program flash memory is empty (unprogrammed), in which case ISP mode is selected. When ENV[2:0] = 011b, ERE mode is se- lected unless the EMPTY bits indicate that the program www.national.com...

  • Page 25: Bus Interface Unit (Biu)

    This gives the accessed memory more time to respond to the transaction request. A hold cycle is inserted at the end of a bus cycle. This holds the data on the data bus for an extended number of clock cy- cles. www.national.com...
  • Page 26 The Post Idle bit controls whether an idle cycle follows the current bus cycle, when the next bus cycle accesses a different zone. No idle cycles are required for on-chip accesses. – No idle cycle (recommended). – Idle cycle inserted. www.national.com...
  • Page 27 A fast read op- zone. – eration takes one clock cycle. A normal read 8-bit bus width. – operation takes at least two clock cycles. 16-bit bus width. – Normal read cycles. – Fast read cycles. www.national.com...

  • Page 28: Wait And Hold States

    0E F000h 0E F1FFh and FF 0000h FF FBFFh, one wait cycle and one preliminary idle cycle is used. No hold cycles are used. The IOCFG register determines the access timing – for the address range FF FB00h FF FBFFh. www.national.com...

  • Page 29: System Configuration Registers

    Main Clock is driven on the ENV1/CPU- CLK pin. SCLKOE The SCLKOE bit controls whether the Slow Clock is driven on the ENV2/SLOWCLK pin. – ENV2/SLOWCLK pin is high impedance. – Slow Clock is driven on the ENV2/SLOW- CLK pin. www.national.com...

  • Page 30: Module Status Register (Mstat)

    This bit is cleared by a SWRESET(CLR) sequence or a power-on re- set. – No software ISP reset has occurred since this bit was last cleared. – A software ISP reset has occurred since this bit was last cleared. www.national.com...

  • Page 31: Flash Memory

    Each bit in the Flash Memory Write Enable (FM0WER and FM1WER) registers enables or disables write access to a corresponding section of flash program memory. Write ac- cess to the flash data memory is controlled by the bits in the Flash Slave Memory Write Enable (FSM0WER) register. By www.national.com...

  • Page 32: Flash Memory Operations

    2. Read the data word by reading out the Flash Memory Word if section write Information Block Data (FMIBDR) or Flash Slave Mem- enable bit is set ory Information Block Data (FSMIBDR) register. and global write Other –0 080h protection is dis- (User Data) abled. www.national.com...
  • Page 33 FMIB- DR or FSMIBDR register. 5. Wait until the FMBUSY bit becomes clear again. 6. Check the Erase Error (EERR) bit in the FMSTAT or FSMSTAT register to confirm successful erase of the block. 7. Clear the MER bit. www.national.com...

  • Page 34: Information Block Words

    Table 15 sum- marizes all possible EMPTY, ISPE, and Boot Area settings and the corresponding start-up operation for each combination. In DEV mode, the EMPTY bit settings are ignored and the CPU always starts executing from address www.national.com...

  • Page 35: Flash Memory Interface Registers

    Table 16 lists the registers. Reload Register FMAR0 FSMAR0 Flash Memory FF F964h FF F764h Auto-Read Register 0 FMAR1 FSMAR1 Flash Memory FF F966h FF F766h Auto-Read Register 1 FMAR2 FSMAR2 Flash Memory FF F968h FF F768h Auto-Read Register 2 www.national.com...
  • Page 36 The address mapping of the register bits is shown below. Logical Address Range – 02 0000h 02 1FFFh – . . . – 03 E000h 03 FFFFh www.national.com...
  • Page 37 – An external debugging tool is the current erases the block that contains the word “owner” of the flash memory interface, so and its associated main block. write accesses by the CPU are inhibited. www.national.com...
  • Page 38 IENPROG bit can be enabled to trigger an in- terrupt when the buffer is ready to receive a new request. – Buffer is ready to receive new erase or write requests. – Buffer is full. No new erase or write re- quests can be accepted. www.national.com...
  • Page 39 FTMEND field specifies a page erase pulse width of 4096 × (FTPER + 1) prescaler output clocks. FTMEND The Flash Timing Module Erase End Delay Count field specifies a delay of 8 × (FTMEND + 1) prescaler output clocks. www.national.com...
  • Page 40 Transceiver power mode dependent on CADR15 The Code Area Start Address (bits 15) con- USB controller status and programming tains the upper bit of the Code Area start ad- of the Function Word. dress. The CADR15 field has a fixed value of www.national.com...

  • Page 41: Dma Controller

    However, only one source at a time can be enabled. If a channel is used for memory block trans- fers, other resources must be disabled. DS005 Figure 3. Direct DMA Cycle Followed by a CPU Cycle www.national.com...

  • Page 42: Operation Modes

    The ADCAn and ADCBn counters are updated accord- values into the ADCAn, ADCBn, and BLTCn registers. ing to the INCA, INCB, ADA, and ADB fields in the 2. The DMASTAT.VLD bit is cleared. DMACNTLn register. 3. The next block transfer is started. www.national.com...

  • Page 43: Software Dma Request

    Block Length Register DMA channel receives a DMA transfer request. When the DMACNTL1 FF F83Ch DMA Control Register DMACNTLn.SWRQ bit is clear, the software DMA transfer request of the corresponding channel is inactive. DMASTAT1 FF F83Eh DMA Status Register www.national.com...
  • Page 44 2 bytes, as selected by the DMACNTLn.TCS bit. INCA field of DMACNTLn register. The upper 8 bits of the ADCAn register are reserved and always clear. Block Length Counter Reserved Device A Address Counter Note: 0000h is interpreted as 2 -1 transfer cycles. www.national.com...
  • Page 45 – Direct transfer (flyby). 00 – Increment ADCBn register by 1. – Indirect transfer (memory-to-memory). 01 – Increment ADCBn register by 2. 10 – Decrement ADCBn register by 1. 11 – Decrement ADCBn register by 2. www.national.com...
  • Page 46 The present transfer is completed and the ADRAn, ADRBn (indirect mode only), and BLTR registers are copied to the ADCAn, ADCBn (indirect mode only), and BLTCn registers. Writing 1 to the VLD bit. www.national.com...

  • Page 47: Interrupts

    Interrupt Enable and IENAM1 FF FE10h peripherals that request the interrupts. The ICU supports Mask Register 1 IRQ0, but in the CP3BT26 it is not connected to any inter- Interrupt Enable and rupt source. IENAM2 FF FE22h Mask Register 2 www.national.com...
  • Page 48 When the ENLCK bit is set, the EN bit is ignored. – NMI interrupts not enabled by this bit (but may be enabled by the EN bit). – NMI interrupts enabled. www.national.com...
  • Page 49 IRQ47, for example IENA47 controls terrupt request. IST47:32 correspond to IRQ47. IRQ47 to IRQ32, respectively. – – Interrupt is disabled. Interrupt is not active. – – Interrupt is enabled. Interrupt is active. www.national.com...

  • Page 50: Maskable Interrupt Sources

    IRQ25 VTUD (VTU Interrupt Request 4) IRQ24 Microwire/SPI RX/TX IRQ23 UART0 TX IRQ22 UART0 CTS IRQ21 Reserved IRQ20 UART1 RX IRQ19 UART1 TX IRQ18 UART2 RX IRQ17 UART2 TX IRQ16 UART3 RX IRQ15 UART3 TX www.national.com...

  • Page 51: Triple Clock And Reset

    Stop Slow Osc Bypass 32 kHz Osc Fast Clock Prescaler 4-Bit System Clock Prescaler Fast Clock Select PLL Clock (x3, x4, or x5) Bypass PLL Good PLL Clock Stop PLL Stop PLL DS006 Figure 4. Triple Clock and Reset Module www.national.com...

  • Page 52: External Crystal Network

    X1CKO The crystal network you choose may require external com- ponents different from the ones specified in this datasheet. In this case, consult with National’s engineers for the com- ponent specifications The crystals and other oscillator components must be placed close to the X1CKI/X1CKO and X2CKI/X2CKO de- vice input pins to keep the printed trace lengths to an abso- lute minimum.

  • Page 53: Main Clock

    When the signal goes inactive, the low-frequency oscillator while the MODE field is modified. starts, and the 6-bit timer counts down from its preset value. When the timer reaches zero, it stops counting and asserts www.national.com...

  • Page 54: System Clock

    Attempting to set the PLLPWD bit while the FCLK bit is clear is ignored. The The value of R should be less than 50K ohms. The RC time constant of the circuit should be 5 times the power supply www.national.com...
  • Page 55 This register must not be modified when the Clock 2 from the Main Clock. The Main Clock System Clock is derived from the PLL Clock. is divided by a value of (ACDIV2 + 1). The System Clock must be derived from the www.national.com...

  • Page 56: Power Management

    It is recommended to keep CPU activity at a minimum by ex- CVSD/PCM On/Off On/Off On/Off Aux 2 Clock ecuting the WAIT instruction to guarantee low power con- sumption in the system. On/Off On/Off On/Off Off* Aux 2 Clock All Others On/Off On/Off System www.national.com...

  • Page 57: Idle Mode

    The DMC and DHC bits and the HCC mechanism have no effect in Active or Halt mode. PLL Power Down Bit: The PLLPWD bit in the CRCTRL register can be used to disable the PLL in all modes. This bit does not affect the high-frequency oscillator. www.national.com...
  • Page 58 Halt mode or when disabled by the mode only if the DMC bit or the CRC- HCC mechanism. TRL.PLLPWD bit is set. – – High-frequency oscillator is also disabled PLL is also disabled if the Bluetooth LLC in Power Save and Idle modes. is idle. www.national.com...

  • Page 59: Switching Between Power Modes

    WAIT instruction. At execution of the WAIT instruction, the device enters the Power Save mode, and the CPU waits for the next interrupt event. In this case, the PMMCR.PSM bit becomes set when it is written, even before the WAIT instruction is executed. www.national.com...
  • Page 60 0 to the PM- ing) so that the hardware can detect the absence of the MCR.DMC bit. Before writing a 0 to the PMMCR.PSM bit, crystal. software must first monitor the PMMSR.OMC bit to deter- mine when the oscillator has stabilized. www.national.com...

  • Page 61: Multi-Input Wake-Up

    MIWU Interrupt 3:0 Encoder MIWU Interrupt 7:4 WUI15 WUI31 WK0EDG WK0PND WK1EDG WK1PND Wake-Up Signal To Power Mgt WK0ENA WK1ENA ... DS218 Figure 9. Multi-Input Wake-Up Module Block Diagram www.national.com...

  • Page 62: Multi-Input Wake-Up Registers

    Wake-Up Pending WK1PCL FF FCAAh Clear Register WUI27 UART2 RXD Module 1 WUI28 UART3 RXD Wake-Up Interrupt WUI29 Reserved WK0IENA FF FC8Ch Enable Register Module 0 WUI30 ADC Done Wake-Up Interrupt WUI31 Reserved WK1IENA FF FCACh Enable Register Module 1 www.national.com...
  • Page 63 WKEN Interrupt disabled. – Interrupt enabled. WKEN The Wake-Up Enable bits enable and disable the MIWU channels. The WKEN15:0 bits cor- respond to the WUI15:0 channels, respective- – MIWU channel wake-up events disabled. – MIWU channel wake-up events enabled. www.national.com...
  • Page 64 01 – Selects MIWU interrupt request 5. 01 – Selects MIWU interrupt request 5. 10 – Selects MIWU interrupt request 6. 10 – Selects MIWU interrupt request 6. 11 – Selects MIWU interrupt request 7. 11 – Selects MIWU interrupt request 7. www.national.com...
  • Page 65 Writing 1 to a bit sets it. – Trigger condition did not occur. WKCL Writing 1 to a bit clears it. – – Trigger condition occurred. Writing 0 has no effect. – Writing 1 clears the corresponding bit in the WK1PD register. www.national.com...

  • Page 66: Programming Procedures

    3. Set the corresponding bit in the WK0PCL or WK1PCL register to clear the pending bit in the WK0PND or WK1PND register. 4. Set the same WK0ENA or WK1ENA bit to re-enable the wake-up function. www.national.com...

  • Page 67: Input/Output Ports

    Each port has an associated set of memory-mapped regis- PxDIR: Port direction register ters used for controlling the port and for holding the port da- PxDIN: Port data input register PxDOUT: Port data output register PxWPU: Port weak pull-up register PxHDRV: Port high drive strength register www.national.com...
  • Page 68 Port F Data Output Register E, F, G, H, or J. For example, “PxDIR register” means any one of the port direction registers: PBDIR, PCDIR, PEDIR, Port F Weak Pull-Up PFWPU FF FCE8h PFDIR, PGDIR, PHDIR, or PJDIR. Register www.national.com...
  • Page 69 PxWPU PxDIR PxWPU The PxWPU bits control whether the weak pull-up is enabled. – Weak pull-up disabled. PxDIR The PxDIR bits select the direction of the cor- – Weak pull-up enabled. responding port pin. – Input. – Output. www.national.com...
  • Page 70 Port Pin PxALTS = 0 PxALTS = 1 WUI23 Reserved UART0 RXD0 Reserved WUI24 Reserved UART0 TXD0 Reserved ASYNC WUI9 UART0 RTS Reserved UART0 CTS Reserved UART0 CKX SRFS TIO1 MDIDO TIO2 MDODI TIO3 MWCS TIO4 TIO5 TIO6 TIO7 www.national.com...

  • Page 71: Open-Drain Operation

    With the direction register bit clear (direction = in), the pin is placed in the TRI-STATE mode. If desired, the internal weak pull-up can be enabled to pull the signal high when the output buffer is in TRI- STATE mode. www.national.com...

  • Page 72: Bluetooth Controller

    LMX5252 data sheet which is available from the PG3/SCLK BDCLK National Semiconductor wireless group. National provides software libraries for using the Bluetooth LLC. Documenta- PG4/SDAT BDDATA tion for the software libraries is also available from National Semiconductor. PG5/SLE BDEN# 15.1 RF INTERFACE X1CKI/BBCLK...

  • Page 73: Serial Interface

    SLE is the alternate function of the general-purpose I/O pin PG5. At reset, this pin is in TRI-STATE mode. Software must enable the alternate function of the PG5 pin to give control over this signal to the RF interface. www.national.com...
  • Page 74 LMX5252. control overhead, which allows fast loading of time-critical registers during normal operation. When the FW bit is set, the 3-bit header may have a value other than 101b, and it is www.national.com...
  • Page 75 101 0 01010 1101110000000100 Write cycle driven by CP3BT26. Data is DC04h. Address is 0Ah. 101 1 01010 First part of read cycle driven by CP3BT26. Address is 0Ah. 0000000000000001 Second part of read cycle driven by LMX5252. Counter value is 1. www.national.com...

  • Page 76: Lmx5251 Power-Up Sequence

    LMX5251 in LMX5251 in Normal Mode DS324 Power-Up Mode DS016 Figure 21. LMX5252 Power States Figure 20. LMX5251 Power-Up Sequence The power-up sequence for a Bluetooth system based on the CP3BT26 and LMX5252 devices is shown in Figure 22. www.national.com...

  • Page 77: Bluetooth Sleep Mode

    HCC signal to the PMM is deasserted. 9. The PMM restarts the 12 MHz Main Clock (and the PLL, if required). The N-counter starts counting. After N + 1 Slow Clock cycles, the Bluetooth clocks (1 MHz www.national.com...

  • Page 78: Bluetooth Shared Data Ram

    Link Control 2 – 02C0h 02FFh Link Control 3 – 0300h 033Fh Link Control 4 – 0340h 037Fh Link Control 5 – 0380h 03BFh Link Control 6 – 03C0h 03FFh Link Control 7 – – 0400h 11FFh Link Payload 0 www.national.com...

  • Page 79: 12-Bit Analog To Digital Converter

    The low-ohmic drivers used for interface to resistive Internal/External Multiplexer—an analog multiplexer touchscreens are controlled by the TOUCH_CFG field. that selects between the output of the Input Multiplexer and the ADCIN external analog input. www.national.com...
  • Page 80 The Done signal is visible to software as the ADC_DONE bit in the ADCRESLT register. The Done signal is also an input to the interrupt controller (IRQ13). The interrupt will be as- serted whenever the FIFO is not empty (but will deassert for www.national.com...

  • Page 81: Touchscreen Interface

    This measurement is used as an indication of the force of pen contact. When 100b is loaded into the TOUCH_CFG field, the TSY+ signal is pulled to VCC and the TSX- signal is pulled to GND, to support measuring RZ. www.national.com...
  • Page 82 ------------------- - 4096 – 3981 RYP RY1   – 610 uV ------------ - ------------------------------ - 2047 Software scaling could be applied to this value if re- quired (as with technique 1, above), but no additional resolution is achieved. www.national.com...

  • Page 83: Adc Operation In Power-Saving Modes

    FREEZE input. When FREEZE is asserted the module will exhibit the following specific be- havior: The automatic clear-on-read function of the result regis- ter (ADCRESLT) is disabled. The FIFO is updated as usual, and an interrupt for a completed conversion can be asserted. www.national.com...
  • Page 84 Driven Low Inactive Sample X Sample Z (1), Driven High Inactive Inactive Driven Low Pre-Pen Down Inactive Driven High Driven Low Inactive Sample Z (2) Weakly Pulled High Inactive Inactive Driven Low Pen-Down Detect Inactive Inactive Inactive inactive Reserved www.national.com...
  • Page 85 ADC conver- sion is in progress. The bit is cleared after the conversion is completed. 0 – ADC is not performing a conversion. 1 – ADC conversion is in progress. www.national.com...
  • Page 86 With a module clock of 12 MHz, the 0 – Automatic mode disabled. maximum delay which can be provided by 1 – Automatic mode enabled. ADC_DIV and ADC_DELAY settings is:   × × ------------------- - 170 us   12 MHz www.national.com...
  • Page 87 ADCRESLT register was last read. mode, this bit is always 0. 1 – An ADC conversion has completed since 1 – In differential mode, - input has a voltage the ADCRESLT register was last read. greater than the + input. www.national.com...

  • Page 88: Random Number Generator (Rng)

    RNDGD register is disabled. System Clock. RNGCST Enable Sample 31-Bit LFSR 16-Bit Shift Register Flip-Flop Fast Osc. Clock Clock Clock (~24 MHz) System Slow Osc. RNGD (~115 kHz) (Unstable) RNGDIVH/RNGDIVL System Sample Strobe Clock Divider DS185 Figure 28. RNG Module Block Diagram www.national.com...

  • Page 89: Random Number Generator Register Set

    1 – RNGD register holds valid data. 0000 83D6h. IMASK The Interrupt Mask bit controls whether an in- terrupt request (IRQ3) will be asserted when valid (random) data is available in the RNGD register. 0 – RNG interrupt disabled. 1 – RNG interrupt enabled. www.national.com...

  • Page 90: Usb Controller

    USB node is in the NodeSuspend state. The MIWU can be USB specifications require that a device must be ready to programmed to generate an edge-triggered interrupt when respond to USB tokens within 10 ms after wake-up or reset. this occurs. www.national.com...

  • Page 91: Endpoint Operation

    Receive FIFO2 with the frame number match logic. EPC4Register Endpoints in different directions programmed with the same endpoint number operate independently. Transmit FIFO3 EPC5 Register Receive FIFO3 EPC6 Register DS049 Figure 29. USB Function Address/Endpoint Decoding www.national.com...
  • Page 92 TXFL is equal to or less than the number specified by the TFWL bit in the TXCn register. TCOUNT The Transmit FIFO Count indicates how many empty bytes can be filled within the transmit FIFO. This value is accessible by software in the TXSn register. www.national.com...

  • Page 93: Usb Controller Registers

    The Receive FIFO Count indicates how many FF FDAEh Mirror Register bytes can be read from the receive FIFO. This value is accessible by software via the RXSn DMACNT FF FDB0h DMA Count Register register. DMAERR FF FDB2h DMA Error Register www.national.com...
  • Page 94 1 – The USB module is enabled. Transmit Data 2 TXD2 FF FDE2h Register Transmit Data 3 TXD3 FF FDF2h Register Receive Status 0 RXS0 FF FDCCh Register Receive Status 1 RXS1 FF FDDCh Register Receive Status 2 RXS2 FF FDECh Register www.national.com...
  • Page 95 All endpoint controllers and the bits TX_EN, LAST, and RX_EN are reset, while all other internal states are frozen. On detection of bus activity, the RESUME bit in the ALTEV register is set. In response, software can cause entry to NodeOperational state. www.national.com...
  • Page 96 1 – Frame timer has either entered an un- locked condition from a locked condition or re-entered a locked condition from an unlocked condition. www.national.com...
  • Page 97 ALT bit in the MAEV register when the respective event in the ALTEV register occurs. Otherwise, setting MAEV.ALT bit is disabled. The ALTMSK register is clear af- ter reset. It provides read/write access from the CPU bus. RESUME RESET SD5 SD3 EOP DMA Reserved www.national.com...
  • Page 98 RX_EV bit in the MAEV register is set. When clear, the corresponding bit in the RXEV register does not cause the RX_EV bit to be set. The RXMSK register pro- vides read/write access. This register is clear after reset. RXOVRRN RXFIFO www.national.com...
  • Page 99 This bit is set by the hardware and is cleared by reading the FNH register. 0 – No condition indicated. 1 – At least two frames were received without an expected frame number, or no valid SOF was received within 12060 bit times. www.national.com...
  • Page 100 0 – The device does not respond to any token in the DMAEV register must be cleared, ex- on the USB bus. cept for NTGL. 1 – The AD field is used for address compar- 0 – Automatic DMA disabled. ison. 1 – Automatic DMA enabled. www.national.com...
  • Page 101 For receiving, the The NTGL bit provides read-only access from DERR bit is equivalent to the RX_ERR bit. For the CPU bus and is cleared after reset. transmitting, the DERR bit is equivalent to the www.national.com...
  • Page 102 USB node to ignore packets re- ceived with errors (as specified in the DERR bit description in the DMAMSK reg- ister). If this bit is set during receive oper- ations, the USB node is automatically flushed and the receive FIFO is reset to www.national.com...
  • Page 103 DATA1 PID to be generated. This bit the CPU bus. After reset this bit is cleared. is not altered by the hardware. 0 – Disable STALL handshakes. 0 – DATA0 PID is used. 1 – Enable STALL handshakes. 1 – DATA1 PID is used. www.national.com...
  • Page 104 This bit is unchanged for 0 – Do not ignore SETUP tokens. zero-length packets. It is cleared when this 1 – Ignore SETUP tokens. register is read. 0 – No ACK was sent. 1 – An ACK was sent. www.national.com...
  • Page 105 If it is clear, the device does not respond to any address, without regard to the EP_EN state.) 0 – Address comparison is disabled. 1 – If the AD_EN bit is also set, address com- parison is enabled. www.national.com...
  • Page 106 If the MAC is currently using the FIFO to transmit, TXRP is reloaded only after the transmission is complete. After reload, this bit is cleared by hardware. 0 – No action. 1 – Reload the saved TXRP. www.national.com...
  • Page 107 The PID such as bit-stuffing or CRC. If this bit is set, and CRC16 are inserted automatically in the software must flush the respective FIFO. transmit data stream. 0 – No receive error occurred. 1 – Receive error occurred. www.national.com...

  • Page 108: Transceiver Interface

    FIFO is equal to or less than the selected warning limit, the RXWARN bit in the FWEV register is set. Table 44 Receive FIFO Warning Limit RFWL Bytes Remaining in FIFO RFWL disabled ≤ 4 ≤ 8 ≤ 16 www.national.com...

  • Page 109: Can Module

    Then, the buffer contents will be copied into the first mes- Remote Frame support sage buffer which accepts the ID of the received message. — Automatic transmission after reception of a Remote Transmission Request (RTR) — Auto receive after transmission of a RTR Acceptance filtering www.national.com...

  • Page 110: Basic Can Concepts

    CAN module responsible for brake lights must not process controlling processor. If any module cannot process infor- this message. mation, it can send an overload frame. www.national.com...
  • Page 111 10000011111 . . . 01111100000 . . . reserved bits (RB1, RB0). The transmitter must be config- unstuffed bit stream ured to send only zeros. Stuffed bit stream 1000001111101 . . . 0111110000010 . . . (stuff bits in bold) www.national.com...
  • Page 112 Arbitration Field Control Field Data Field CRC Field END OF FRAME d d d IDENTIFIER IDENTIFIER DATA 28 ... 18 17 ... 0 LENGTH CODE Bit Stuffing Note: d = dominant DS021 r = recessive Figure 37. Extended Data Frame www.national.com...
  • Page 113 Control Field Cyclic Redundancy Check Field (CRC) Acknowledgment field (ACK) End of Frame (EOF) Note that the DLC must have the same value as the corre- sponding data frame to prevent contention on the bus. The RTR bit is “recessive”. www.national.com...
  • Page 114 The inter- frame space consists of a minimum of three bit fields de- pending on the error state of the node. www.national.com...
  • Page 115 Once the CAN module is enabled, it waits for 11 consecu- ture. See System Start-Up and Multi-Input Wake-Up on tive recessive bits to synchronize with the bus. After that, the page 140. CAN module becomes error active and can participate in www.national.com...
  • Page 116 An ACK-error occurs in an error passive device and no the “bus off” state due to such a condition. “dominant” bits are detected while sending the passive error flag. This does not lead to an increment of the TEC. www.national.com...
  • Page 117 This is interpreted as the SOF. It restarts the internal logic. Soft synchronization is performed during the reception of a bit stream to lengthen or shorten the internal bit time. De- www.national.com...

  • Page 118: Message Transfer

    PSC, TSEG1, and TSEG2 as follows: A dedicated acceptance filtering procedure enables soft- ware to configure each buffer to receive only a single mes- sage ID or a group of messages. One buffer uses an www.national.com...

  • Page 119: Acceptance Filtering

    1 or 0. one valid frame. The buffer will be unlocked again after the CPU has read the data and has written RX_READY in the www.national.com...

  • Page 120: Receive Structure

    0. For example, if the mes- sage is accepted by buffer 5, then at the time the message will be copied, the RX request is cleared and the CAN mod- ule will not try to match the frame to any subsequent buffer. www.national.com...
  • Page 121 If the status is changed while the BUSY bit is asserted, the status is updated by the CAN module as shown in Table 46. The buffer states are indicated and controlled by the ST[3:0] bits in the CNSTAT register (see Buffer Status/Control Reg- www.national.com...
  • Page 122 During the copy process the buffer will buffer has received a message and entered the again be RX_BUSYx for a short time, but in this case the RX_FULL state (see also Interrupts on page 125). In www.national.com...

  • Page 123: Transmit Structure

    If more than one buffer is scheduled for transmission, the buffer object. In all cases, writing to the BUSY bit will be ig- priority is built by the message buffer number and the prior- nored. ity code in the CNSTAT register. The 8-bit value of the prior- www.national.com...
  • Page 124 Write_buffer Write TX_NOT_ACTIVE TX_BUSYx? Write ID/data Write TX_ONCE TX_ONCE_RTR TX_RTR Exit Highest DS041 Note: If two buffers have the same priority (PRI), the buffer Figure 57. Buffer Write Routine with the lower buffer number will have the higher priority. www.national.com...

  • Page 125: Interrupts

    — Successful transmission of a data frame. (Buffer state ister. The pending flags of the message buffer are located in changes from TX_ONCE to TX_NOT_ACTIVE or the CIPND register (read only) and can be cleared by reset- RX_READY.) ting the flags in the CICLR registers. www.national.com...

  • Page 126: Time Stamp Counter

    CTMR value during the ACK slot of a message (as above), Buffer 4 and then the CTMR is reset to 0000b. Synchronization can be enabled or disabled using the CGCR.TSTPEN bit. Buffer 5 Buffer 6 Buffer 7 Buffer 8 Buffer 9 www.national.com...

  • Page 127: Memory Organization

    Buffer Address Register 0E F0XEh XI[28:18]/ID[10:0] XI[17:15] /RTR 0E F0XCh XI[14:0] 0E F0XAh DATA0 Data1[7:0] Data2[7:0] 0E F0X8h DATA1 Data3[7:0] Data4[7:0] 0E F0X6h DATA2 Data5[7:0] Data6[7:0] 0E F0X4h DATA3 Data7[7:0] Data8[7:0] 0E F0X2h TSTP TSTP[15:0] 0E F0X0h CNSTAT Reserved www.national.com...

  • Page 128: Can Controller Registers

    0E F110h Clear Register CAN Interrupt Code CICEN 0E F112h Enable Register CAN Status CSTPND 0E F114h Pending Register CAN Error CANEC 0E F116h Counter Register CAN Error CEDIAG 0E F118h Diagnostic Register CTMR 0E F11Ah CAN Timer Register www.national.com...
  • Page 129 TX_BUSY2 (Indicates that a buffer is scheduled for trans- mission or is actively transmitting; it can be due to one of two cases: a message is pending for transmission or is cur- rently transmitting, or an automated answer is pending for transmission or is currently transmitting.) www.national.com...
  • Page 130 0E F0XEh ID[10:0] RTR IDE Don’t Care 0E F0XCh Don’t Care 0E F0XAh DATA0 Data1[7:0] Data2[7:0] 0E F0X8h DATA1 Data3[7:0] Data4[7:0] 0E F0X6h DATA2 Data5[7:0] Data6[7:0] 0E F0X4h DATA3 Data7[7:0] Data8[7:0] 0E F0X2h TSTP TSTP[15:0] 0E F0X0h CNSTAT Reserved www.national.com...
  • Page 131 0 – Message is a data frame. 1 – Message is a remote frame. The ID field is used to build the 29-bit identifier of an extended frame. www.national.com...
  • Page 132 0 – Message is a data frame. 1 – Message is a remote frame. The ID field is used to build the 29-bit identifier of an extended frame. The ID[28:18] field is used for the 11 standard frame identifier bits. www.national.com...
  • Page 133 The buffer will be unlocked again by writing RX_READY in the buffer status register, i.e., after reading data. 0 – Lock function is disabled for all buffers. 1 – Lock function is enabled for all buffers. www.national.com...
  • Page 134 ID. However, the CAN module does not ac- knowledge message sent itself. Therefore, the CAN module will send an error frame when no other device connected to the bus has acknowledged the message. 0 – No loopback. 1 – Loopback enabled. www.national.com...
  • Page 135 (see Table 58). Table 58 SJW Settings Synchronization Jump Width (SJW) 1 time quantum 2 time quanta 3 time quanta 4 time quanta Note: The settings of SJW must be configured to be small- er or equal to TSEG1 and TSEG2 www.national.com...
  • Page 136 2 time quanta Global Mask GM[28:18] RTR IDE GM[17:0] XRTR 3 time quanta Standard ID[10:0] RTR IDE Unused 4 time quanta Frame Extended 5 time quanta ID[28:18] SRR IDE ID[17:0] Frame 6 time quanta 7 time quanta 8 time quanta www.national.com...
  • Page 137 For exam- ple, IPND14 corresponds to buffer14, and IPND0 corresponds to buffer0. 0 – No interrupt pending for the correspond- ing message buffer. 1 – Message buffer has generated an inter- rupt. www.national.com...
  • Page 138 1 – Message buffer interrupt pending is indi- 1000 Buffer 7 cated in the interrupt code. 1001 Buffer 8 1010 Buffer 9 1011 Buffer 10 1100 Buffer 11 1101 Buffer 12 1110 Buffer 13 1111 Buffer 14 www.national.com...
  • Page 139 0 – No CRC error occurred. EXTENDED 1 – CRC error occurred. 1011 The Monitor bit shows the bus value on the ARBITRATION CANRX pin as sampled by the CAN module at 1100 R1/R0 the time of the error. www.national.com...

  • Page 140: System Start-Up And Multi-Input Wake-Up

    In this case, the CAN module can be disabled before entering the reduced-power mode. After waking up, software must enable the CAN module again. All configuration and buffer registers still contain the same data they held before the reduced-power mode was entered. www.national.com...
  • Page 141 ID bits of the received message can occur in the application.) need to pass through the acceptance filter. The same ap- plies to transmitting remote frames and switching to receive the corresponding data frames. www.national.com...

  • Page 142: Usage Hint

    When these conditions occur, the frame sent by the CAN module will be copied into the next receive buffer available for the identifier ID_RX_TX. If a frame with an identifier different to ID_RX_TX is sent or received in between events 1 and 2, the problem does not occur. www.national.com...

  • Page 143: Advanced Audio Interface

    In synchronous mode, ers. this signal is used as frame sync by both the transmitter and receiver. The frame sync signal may be generated internally, or it may be provided by an external source. www.national.com...
  • Page 144 There is one DMA transmit register (ATDRn) for each of the I/O (TXDSA0 = 0), all data to be transmitted is read from the maximum four data slots. Each slot can be configured inde- transmit FIFO. An IRQ is asserted as soon as the number pendently. www.national.com...
  • Page 145 DMA transmit register (ATDRn). A DMA request is asserted to the DMA controller when the ATDRn register is empty. Figure 68 illustrates the data flow for IRQ and DMA support in network mode, using four slots per frame and DMA sup- www.national.com...

  • Page 146: Bit Clock Generation

    PCM data word has been transferred. The required bit clock rate f can be calculated by the following equation: = n × f × Data Length = 2 × 8 kHz × 16 = 256 kHz Sample www.national.com...
  • Page 147 FIFO is empty. When an additional read operation ated internally, or they can be supplied by an external from the FIFO to ATSR is performed (while the FIFO is al- source. ready empty), a transmit FIFO underrun occurs. In this www.national.com...

  • Page 148: Communication Options

    FIFO or DMA receive register which edge of the shift clock after the negative edge on the frame were received during the assigned time slots. A receive in- sync pulse. terrupt or DMA request is initiated when this occurs. www.national.com...
  • Page 149 Short Frame Sync Pulse Long Frame Sync Pulse DS156 Figure 71. Short and Long Frame Sync Pulses ACD2 ACD1 ACD0 Audio Control 13-bit PCM Data Word Bits 16-bit Slot DS161 Figure 72. Audio Slot with Audio Control Data www.national.com...
  • Page 150 ARSR register. This mode Output Enable may be used for development, but it also allows testing the transmit and receive path without external circuitry, for ex- ample during Built-In-Self-Test (BIST). DS241 Figure 74. CP3BT26/ISDN Controller Connections www.national.com...

  • Page 151: Audio Interface Registers

    Audio Interrupt Status AISCR FF FD56h and Control Register Audio Receive Status ARSCR FF FD58h and Control Register Audio Transmit Status ATSCR FF FD5Ah and Control Register Audio Clock Control ACCR FF FD5Ch Register Audio DMA Control ADMACR FF FD5Eh Register www.national.com...
  • Page 152 In 16-bit mode, the Audio Receive DMA High data word. In 8-bit mode, the ATDH field is ig- Byte field receives the upper byte of the audio nored. data word copied from ARSR. In 8-bit mode, the ARDH register holds undefined data. www.national.com...
  • Page 153 13 bit clocks Network mode 14 bit clocks 15 bit clocks 16 bit clocks The Inverted Frame Sync bit controls the po- larity of the frame sync signal. 0 – Active-high frame sync signal. 1 – Active-low frame sync signal. www.national.com...
  • Page 154 TXEIP bit. receive error interrupt will be generated. 0 – Writing a 0 to the TXEIC bit is ignored. 0 – Receive error interrupt disabled. 1 – Writing a 1 clears the TXEIP bit. 1 – Receive error interrupt enabled. www.national.com...
  • Page 155 Multiple slots may be en- abled. If the frame consists of less than 4 slots, the RXSA bits for unused slots are ig- nored. For example, if a frame only consists of 2 slots, RXSA bits 2 and 3 are ignored. www.national.com...
  • Page 156 If the frame consists of less than 4 slots, the TXSA bits for unused slots are ignored. For example, if a frame only consists of 2 slots, TXSA bits 2 and 3 are ignored. The fol- lowing table shows the slot assignment scheme. www.national.com...
  • Page 157 DMA controller. If the RMDn bit is set for an assigned slot n (RXDSAn = 1), a DMA request n is asserted, when the ARDRn is full. If the RXDSAn bit for a slot is clear, the RMDn bit is www.national.com...

  • Page 158: Cvsd/Pcm Conversion Module

    On the PCM data side there is double buffering, and on the aligned 13-bit linear data format with the three LSBs un- CVSD side there is an eight word (8 × 16-bit) FIFO for the used. read and write paths. www.national.com...

  • Page 159: Cvsd Conversion

    CVSD In FIFO. (The DMA controller 250 µs and writes a new PCM sample into the PCMOUT can write one new 16-bit CVSD data word into the CVSD buffer every 125 µs. If the previous PCM data has not yet In FIFO.) www.national.com...

  • Page 160: Freeze

    It is double-buffered, providing a 125 µs period for an inter- LOGIN FF FC28h Data Input Register rupt or DMA request to respond. After reset the PCMOUT register is clear. Logarithmic PCM LOGOUT FF FC2Ah Data Output Register Linear PCM LINEARIN FF FC2Ch PCMOUT Data Input Register www.national.com...
  • Page 161 DMA control for reading PCM data from the PCMOUT register. If clear, DMA sup- 15 14 port is disabled. After reset, this bit is clear. 0 – PCM output DMA disabled. Res. RESOLUTION PCMCONV CVSDCONV DMAPI 1 – PCM output DMA enabled. www.national.com...
  • Page 162 The CVNE bit is cleared when the When the FIFO holds 7 or 8 words of data, the CVSTAT register is read. CVOUTST field will read as 111b. 0 – CVSD In FIFO is not nearly empty. 1 – CVSD In FIFO is nearly empty. www.national.com...

  • Page 163: Uart Modules

    The Control and Error Detection block contains the UART cess of start bit detection and bit sampling. control registers, control logic, error detection circuit, parity generator/checker, and interrupt generation logic. The con- trol registers and control logic determine the data format, www.national.com...
  • Page 164 Transmitter Baud Clock Flow Control System Clock Logic Control and Baud Rate Error Detection Generator Parity Generator/Checker Baud Clock Receiver DS060 Figure 76. UART Block Diagram Sample Sample DATA (LSB) STARTBIT Sample DATABIT DS061 Figure 77. UART Asynchronous Communication www.national.com...
  • Page 165 CKX pin or the internal baud parity bit generation is enabled by setting the UPEN bit, a rate generator. In the latter case, the clock signal is placed on the CKX pin as an output. www.national.com...
  • Page 166 22.2.7 Interrupts Table 69 Prescaler Factors The UART is capable of generating interrupts on: Prescaler Select Prescaler Factor Receive Buffer Full 00000 No clock Receive Error Transmit Buffer Empty 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 www.national.com...
  • Page 167 9-bit data format. Parity generation and checking are en- abled and disabled using the PEN bit in the UnFRS register. The UPSEL bits in the UnFRS register are used to select odd, even, or no parity. www.national.com...

  • Page 168: Uart Registers

    FF F26Ah Register 1 UART1 Status U1STAT FF F226h Register UART3 Status U3STAT FF F266h Register UART1 Interrupt Con- U1ICTRL FF F224h trol Register UART3 Interrupt Con- U3ICTRL FF F264h trol Register UART1 Oversample U1OVR FF F230h Rate Register www.national.com...
  • Page 169 UnBAUD register. is omitted and the UPSEL field is ignored. 00 – Odd parity. 01 – Even parity. 10 – No parity, transmit 1 (mark). 11 – No parity, transmit 0 (space). www.national.com...
  • Page 170 UPE, UFE, and UDOE bits are all 0. Enabling transmit DMA automatically disables 0 – No receive error occurred. transmit interrupts, without regard to the state 1 – Receive error occurred. of the UETI bit. 0 – Transmit DMA disabled. 1 – Transmit DMA enabled. www.national.com...
  • Page 171 CTS input has changed state since the CPU last read this register. This functionality 1101 is only available for the UART0 module. 0 – No change since last read. 1110 1 – State has changed since last read. 1111 www.national.com...

  • Page 172: Baud Rate Calculations

    9600 Note that the percent error is much lower than would be pos- sible without the non-integer prescaler factor. Error greater than 3% is marginal and may result in unreliable operation. Refer to Table 71 below for more examples. www.national.com...
  • Page 173 0.16 1.36 345600 15.5 0.44 0.79 0.79 460800 0.16 0.16 0.16 1.36 576000 0.79 0.79 0.79 0.79 691200 0.79 0.79 0.79 806400 0.04 0.79 0.79 921600 0.16 0.16 0.16 1105920 1.36 1.36 0.47 1382400 0.79 0.79 1536000 0.79 2.34 www.national.com...
  • Page 174 7200 0.04 0.44 15.5 0.44 0.79 9600 0.16 0.16 0.16 0.16 14400 0.16 15.5 0.44 0.79 0.79 19200 0.16 0.16 0.16 0.16 38400 0.16 0.16 0.16 0.16 56000 0.79 0.79 0.79 115200 0.16 0.79 128000 2.34 2.34 230400 0.16 www.national.com...

  • Page 175: Microwire/Spi Interface

    23.0 Microwire/SPI Interface Microwire/Plus is a synchronous serial communications Programmable operation as a Master or Slave protocol, originally implemented in National Semiconduc- Programmable shift-clock frequency (master only) ® tor's COP8 and HPC families of microcontrollers to mini- Programmable 8- or 16-bit mode of operation...
  • Page 176 MSK clock. When data are shifted out on MDODI (master mode) or MDIDO (slave mode) on the trail- ing edge of MSK, bit 14 (16-bit mode) is shifted out on the first trailing edge of MSK. www.national.com...

  • Page 177: Master Mode

    End of Transfer Shift Bit 0 Data Out MSB - 1 MSB - 2 Bit 1 (LSB) Sample Point Bit 0 Data In MSB - 1 MSB - 2 Bit 1 (LSB) DS072 Figure 88. Alternate Mode (SCIDL = 1) www.national.com...

  • Page 178: Slave Mode

    Overrun while both the shifter and the read buffer were full. Figure 89 illustrates the interrupt generation logic of this module. OVR = 1 MWSPI RBF = 1 Interrupt BSY = 0 DS073 Figure 89. MWSPI Interrupts www.national.com...

  • Page 179: Microwire Interface Registers

    In the echo back mode, MDODI is transmitted (ech- oed back) on MDIDO if the MWDAT register does not contain any valid data. With the echo back function disabled, the data held in the www.national.com...
  • Page 180 Writing a 0 to this bit position has no effect. No other bits in the MWSTAT register are affected by a write operation to the register. 0 – No receive overrun error has occurred. 1 – Receive overrun error has occurred. www.national.com...

  • Page 181: Access.bus Interface

    In addition to the first Start Condition, a repeated Start Con- dition can be generated in the middle of a transaction. This allows another device to be accessed, or a change in the di- rection of the data transfer. www.national.com...
  • Page 182 When an abort occurs during the address transmission, the master that identifies the conflict should give up the bus, switch to slave mode, and continue to sample SDA to see if it is being addressed by the winning master on the AC- CESS.bus. www.national.com...

  • Page 183: Acb Functional Description

    ST.BER and ACBST.NEGACK bits are cleared), the ACBST.STASTR bit is set. In this case, the ACB stalls any further ACCESS.bus operations (i.e., holds SCL low). If the ACBCTL1.INTE bit is set, it also sends an interrupt to the core. www.national.com...
  • Page 184 Stop Condition is detected, the BER bit is set and the by issuing a Start Condition and sends an address MATCH and GMATCH bits are cleared, causing the module field; then issue a Stop Condition to synchronize all the to be an unaddressed slave. slaves. www.national.com...

  • Page 185: Access.bus Interface Registers

    Writing 1 to the STASTR Register 2 bit clears it. It is also cleared when the module is disabled. Writing 0 to the STASTR bit has no effect. 0 – No stall after start condition. 1 – Stall after successful start. www.national.com...
  • Page 186 7-bit address in the ACBADDR2 register. It is cleared by Start Condition or re- peated Start and Stop Condition (including il- legal Start or Stop Condition). 0 – No address match occurred. 1 – Address match occurred. www.national.com...
  • Page 187 The Stop bit in master mode generates a Stop Condition that completes or aborts the current message transfer. This bit clears itself after the Stop condition is issued. 0 – Writing 0 has no effect. 1 – Writing 1 generates a Stop condition. www.national.com...
  • Page 188 ACB is stalled after the address byte. expansion of this field, with the remaining 7 When the STASTRE bit is clear, the ACB- bits being held in the ACBCTL2 register. ST.STASTR bit is always clear. 0 – No stall after start. 1 – Stall-after-start enabled. www.national.com...

  • Page 189: Usage Hints

    3 and 4 until the SDA signal is released. 1 – Address matching enabled. 5. Clear the BB bit. This enables the START bit to be ex- ecuted. Continue according to “Bus Idle Error Recov- ery” on page 184. www.national.com...
  • Page 190 Timeout = 1000; /* Set timeout while (!(acb->ACBst & ACBSDAST) && Timeout--); if (!Timeout) /* Timed out?? /* YES - return error return (ACBERR_TIMEOUT); *rcv++ acb->ACBsda; /* NO - Read byte from Recv register /* Adjust current address placeholder NextAddress++; www.national.com...
  • Page 191 KBD_OUT |= BIT0; // OScope marker if (!Timeout) /* If timeout, signal error return (ACBERR_TIMEOUT); /* Or if Slave does not reply, report busy/error else if (acb->ACBst & ACBNEGACK) return (ACBERR_NEGACK); /* Otherwise return success else { return (ACB_NOERR); www.national.com...

  • Page 192: Timing And Watchdog Module

    If software loads the TWMT0 register with a new value, the timer uses that value the next time that it reloads the 16-bit timer register (in other words, after reaching zero). Software www.national.com...

  • Page 193: Watchdog Operation

    If the TWCFG register is itself locked, it remains locked until the device is reset. Any other locked registers also remain locked until the device is reset. This feature prevents a run- away program from tampering with the programmed Watch- dog function. www.national.com...
  • Page 194 5Ch to the WDSDM register. 0 – Write a count value to the WDCNT regis- ter to service the Watchdog timer. 1 – Write 5Ch to the WDSDM register to ser- vice the Watchdog timer. www.national.com...

  • Page 195: Watchdog Programming Procedure

    6. Service the Watchdog by periodically writing the value 5Ch to the WDSDM register at an appropriate rate. Servicing must occur at least once per period pro- grammed into the WDCNT register, but no more than once in a single Watchdog input clock cycle. www.national.com...

  • Page 196: Multi-Function Timer

    No Clock Prescaler Register TPRSC Counter 1 Counter 1 Clock Clock Select Reset Prescaled Clock 5-Bit System Prescaler Counter Clock Pulse Accumulator Counter 2 Counter 2 Clock Clock Select External Event Synchr. DS082 Figure 98. Multi-Function Timer Clock Source www.national.com...

  • Page 197: Timer Operating Modes

    Mode will still work, as long as the external event Section 26.5. pulses are at least the size of the whole slow-clock period. Using the prescaled System Clock will also work, but at a much slower rate than the original System Clock. www.national.com...
  • Page 198 TAIEN Timer 1 Timer/Counter 1 Clock TCNT1 TAEN Underflow Timer Interrupt B TBIEN Reload B = Time 2 TBPND TCRB Timer 2 Timer/Counter 2 Timer Clock TCNT2 Interrupt D TDIEN TDPND Clock Selector DS084 Figure 100. Processor-Independent PWM Mode www.national.com...
  • Page 199 Timer 1 Timer/Counter 1 Clock TCNT1 Underflow Timer Interrupt 1 TCIEN Preset TBEN Capture B TCRB TBPND Timer Interrupt 1 TBIEN TDPND Timer 2 Timer/Counter 2 Clock TnCNT2 Underflow Timer Interrupt 2 TDIEN DS085 Figure 101. Dual-Input Capture Mode www.national.com...
  • Page 200 Reload A TAPND TCRA Timer Interrupt 1 Underflow TAIEN Timer 1 Timer/Counter 1 Clock TCNT1 TAEN Reload B TCRB Timer Interrupt 2 Underflow TDIEN Timer 2 Timer/Counter 2 TDPND Clock TCNT2 Clock Selector DS086 Figure 102. Dual-Independent Timer/Counter Mode www.national.com...
  • Page 201 Interrupt 1 Underflow TAIEN Timer 1 Timer/Counter 1 Clock TCNT1 TAEN Timer Interrupt 1 TBIEN TBPND Capture B TCRB Preset TBEN TDPND Timer 2 Timer/Counter 2 Clock TnCNT2 Timer Interrupt 2 TDIEN DS087 Figure 103. Input Capture Plus Timer Mode www.national.com...

  • Page 202: Timer Interrupts

    TBEN = 0 Accumulate Input TCRB Accumulate Input TCRB TAEN = X Ext. Event or Pulse Capture TCNT1 into Ext. Event or Pulse Capture TCNT2 into TBEN = 1 Accumulate Input TCRB and Preset Accumulate Input TCRB and Preset TCNT1 TCNT2 www.national.com...

  • Page 203: Timer Registers

    TCNT1 26.5.4 Timer/Counter 2 Register (TCNT2) The TCNT2 register is a word-wide, read/write register that holds the current count value for Timer/Counter 2. The reg- ister contents are not affected by a reset and are unknown after power-up. TCNT2 www.national.com...
  • Page 204 TB is low. 0 – TB input is sensitive to falling edges (high to low transitions). 1 – TB input is sensitive to rising edges (low to high transitions). www.national.com...
  • Page 205 A, B, C, and 0 – Writing a 0 has no effect. D, see Table 77. 1 – Writing a 1 clears the TDPND bit. 0 – Condition A interrupts disabled. 1 – Condition A interrupts enabled. www.national.com...

  • Page 206: Versatile Timer Unit (Vtu)

    Capture Compare Capture DTYCAP1 DTYCAP2 DTYCAP3 DTYCAP4 I/O Control I/O Control I/O Control I/O Control I/O Control I/O Control I/O Control I/O Control TIO1 TIO2 TIO3 TIO4 TIO5 TIO6 TIO7 TIO8 DS088 Figure 104. Versatile Timer Unit Block Diagram www.national.com...
  • Page 207 TxRUN bits of a timer subsystem are clear. Any writes to the value matches the previous period value or the timer is counter register while either timer is running will be ignored. stopped. www.national.com...
  • Page 208 PWM wave- duty cycle measurement of an external signal. forms or two PWM waveforms of opposite polarities. This can be accomplished by setting the two PxPOL bits of the respective timer subsystem to either identical or opposite values. www.national.com...
  • Page 209 16-bit PWM Mode Capture Mode IxAPD Low Byte Duty Cycle match Duty Cycle match Capture to PERCAPx IxBPD Low Byte Period match Period match Capture to DTYCAPx IxCPD High Byte Duty Cycle match Counter Overflow IxDPD High Byte Period match www.national.com...

  • Page 210: Vtu Registers

    Register concatenated and operate as a single 16-bit counter. The counter may be start- ed or stopped with the lower of the two TxRUN bits, i.e., T1RUN, T3RUN, T5RUN, and T7RUN. The TIOx pins will function as capture inputs. www.national.com...
  • Page 211 IxBPD bit will be updated regardless of the duty cycle value. value of the IxBEN bit. 0 – Disable system interrupt request for the IxBPD pending bit. 1 – Enable system interrupt request for the Ix- BPD pending bit. www.national.com...
  • Page 212 4. The counter of timer subsystem is 0 – No interrupt pending. incremented each time when the clock pres- 1 – Timer interrupt condition occurred. caler compare value matches the value of the clock prescaler counter. The division ratio is equal to (C4PRSC + 1). www.national.com...
  • Page 213 Reading may take place at any time and will return the most recent value which was written. The PERCAPx registers are cleared at reset. PCAPx www.national.com...

  • Page 214: Register Map

    Byte 0E F1A7h Read/Write M_COUNTER_2 Byte 0E F1A8h Read/Write N_COUNTER_0 Byte 0E F1AAh Write-Only N_COUNTER_1 Byte 0E F1ABh Write-Only BT_CLOCK_WR_0 Byte 0E F1ACh Write-Only BT_CLOCK_WR_1 Byte 0E F1ADh Write-Only BT_CLOCK_WR_2 Byte 0E F1AEh Write-Only BT_CLOCK_WR_3 Byte 0E F1AFh Write-Only www.national.com...
  • Page 215 Read/Write RXMSK Byte FF FD9Ah Read/Write NAKEV Byte FF FD9Ch Read/Write NAKMSK Byte FF FD9Eh Read/Write FWEV Byte FF FDA0h Read/Write FWMSK Byte FF FDA2h Read/Write Byte FF FDA4h Read/Write Byte FF FDA6h Read/Write DMACNTRL Byte FF FDA8h Read/Write www.national.com...
  • Page 216 Byte FF FDF0h Read/Write TXD3 Byte FF FDF2h Read/Write TXS3 Byte FF FDF4h Read/Write TXC3 Byte FF FDF6h Read/Write EPC6 Byte FF FDF8h Read/Write RXD3 Byte FF FDFAh Read/Write RXS3 Byte FF FDFCh Read/Write RXC3 Byte FF FDFEh Read/Write www.national.com...
  • Page 217 0E F0C0h– Same register layout CMB12 8-word Read/Write XXXXh 0E F0CFh as CMB0. 0E F0D0h– Same register layout CMB13 8-word Read/Write XXXXh 0E F0DFh as CMB0. 0E F0E0h– Same register layout CMB14 8-word Read/Write XXXXh 0E F0EFh as CMB0. www.national.com...
  • Page 218 Read/Write 0000h DMASTAT0 Byte FF F81Eh Read/Write Double ADCA1 FF F820h Read/Write 0000 0000h Word Double ADRA1 FF F824h Read/Write 0000 0000h Word Double ADCB1 FF F828h Read/Write 0000 0000h Word Double ADRB1 FF F82Ch Read/Write 0000 0000h Word www.national.com...
  • Page 219 Read/Write 0000h DMASTAT3 Byte FF F87Eh Read/Write Bus Interface Unit BCFG Byte FF F900h Read/Write IOCFG Word FF F902h Read/Write 069Fh SZCFG0 Word FF F904h Read/Write 069Fh SZCFG1 Word FF F906h Read/Write 069Fh SZCFG2 Word FF F908h Read/Write 069Fh www.national.com...
  • Page 220 Word FF F740h Read/Write 0000h FSMIBDR Word FF F742h Read/Write 0000h FSM0WER Word FF F744h Read/Write 0000h FSMCTRL Word FF F74Ch Read/Write 0000h FSMSTAT Word FF F74Eh Read/Write 0000h FSMPSR Byte FF F750h Read/Write FSMSTART Byte FF F752h Read/Write www.national.com...
  • Page 221 Word FF FC3Ch Read Only 0000h CVENCPR Word FF FC3Eh Read Only 0000h Triple Clock + Reset CRCTRL Byte FF FC40h Read/Write 00X0 0110b PRSFC Byte FF FC42h Read/Write PRSSC Byte FF FC44h Read/Write PRSAC Byte FF FC46h Read/Write www.national.com...
  • Page 222 FF FB00h Read/Write PBDIR Byte FF FB02h Read/Write PBDIN Byte FF FB04h Read Only PBDOUT Byte FF FB06h Read/Write PBWPU Byte FF FB08h Read/Write PBHDRV Byte FF FB0Ah Read/Write PBALTS Byte FF FB0Ch Read/Write PCALT Byte FF FB10h Read/Write www.national.com...
  • Page 223 FF F322h Read/Write PHDIN Byte FF F324h Read Only PHDOUT Byte FF F326h Read/Write PHWPU Byte FF F328h Read/Write PHHDRV Byte FF F32Ah Read/Write PHALTS Byte FF F32Ch Read/Write PJALT Byte FF F340h Read/Write PJDIR Byte FF F342h Read/Write www.national.com...
  • Page 224 ISTAT0 Word FF FE0Ah Read Only 0000h ISTAT1 Word FF FE0Ch Read Only 0000h ISTAT2 Word FF FE20h Read Only 0000h IENAM0 Word FF FE0Eh Read/Write FFFFh IENAM1 Word FF FE10h Read/Write FFFFh IENAM2 Word FF FE22h Read/Write FFFFh www.national.com...
  • Page 225 FF F226h Read only U1FRS Byte FF F228h Read/Write U1MDSL1 Byte FF F22Ah Read/Write U1BAUD Byte FF F22Ch Read/Write U1PSR Byte FF F22Eh Read/Write U1OVR Byte FF F230h Read/Write U1MDSL2 Byte FF F232h Read/Write U1SPOS Byte FF F234h Read/Write www.national.com...
  • Page 226 FF F266h Read only U3FRS Byte FF F268h Read/Write U3MDSL1 Byte FF F26Ah Read/Write U3BAUD Byte FF F26Ch Read/Write U3PSR Byte FF F26Eh Read/Write U3OVR Byte FF F270h Read/Write U3MDSL2 Byte FF F272h Read/Write U3SPOS Byte FF F274h Read/Write www.national.com...
  • Page 227 Word FF FF42h Read/Write TCRB Word FF FF44h Read/Write TCNT2 Word FF FF46h Read/Write TPRSC Byte FF FF48h Read/Write TCKC Byte FF FF4Ah Read/Write TCTRL Byte FF FF4Ch Read/Write TICTL Byte FF FF4Eh Read/Write TICLR Byte FF FF50h Read/Write www.national.com...
  • Page 228 Read/Write 0000h ADCRESLT Word FF F3CAh Read Only 0000h ADCSMBC0 Word FF F3CEh Read/Write 1483h ADCSMBC1 Word FF F3D0h Read/Write 24E6h ADCSMBC2 Word FF F3D2h Read/Write 2508h ADCSMBC3 Word FF F3D4h Read/Write 314Ah ADCSMSH Word FF F3D6h Read/Write 01A2h www.national.com...
  • Page 229 Access Value After Register Name Size Address Comments Type Reset RNGCST Word FF F280h Read/Write 0000h RNGD Word FF F282h Read/Write 0000h RNGDIVH Word FF F284h Read/Write 0000h RNGDIVL Word FF F286h Read/Write 0000h www.national.com...

  • Page 230: Register Bit Fields

    SPI_DATA_ SPI_MODE_CONFIG Reserved SPI_CLK_CONF[1:0] CONF _CONF3 _CONF2 CONF1 M_COUNTER_0 M_COUNTER[7:0] M_COUNTER_1 M_COUNTER[15:8] M_COUNTER_2 Reserved M_COUNTER[20:16] N_COUNTER_0 N_COUNTER[7:0] N_COUNTER_1 Reserved N_COUNTER[9:8] BT_CLOCK_WR_0 BT_CLOCK_WR[7:0] BT_CLOCK_WR_1 BT_CLOCK_WR[15:8] BT_CLOCK_WR_2 BT_CLOCK_WR[23:16] BT_CLOCK_WR_3 Reserved BT_CLOCK_WR[27:24] WTPTC_1SLOT[7:0] WTPTC_1SLOT[7:0] WTPTC_1SLOT[15:8] WTPTC_1SLOT[15:8] WTPTC_3SLOT[7:0] WTPTC_3SLOT[7:0] WTPTC_3SLOT[15:8] WTPTC_3SLOT[15:8] WTPTC_5SLOT[7:0] WTPTC_5SLOT[7:0] www.national.com...
  • Page 231 Reserved USBEN AD_EN NFSR Reserved MAEV INTR RX_EV FRAME TX_EV WARN MAMSK INTR RX_EV FRAME TX_EV WARN ALTEV RESUME RESET CLKSTB Reserved ALTMSK RESUME RESET CLKSTB Reserved TXEV TXUDRRUN TXFIFO TXMSK TXUDRRUN TXFIFO RXEV RXOVRRUN RXFIFO RXMSK RXOVRRUN RXFIFO www.national.com...
  • Page 232 RX_ERR SETUP TOGGLE RX_LAST RCOUNT IGN_ RXC1 Reserved RFWL Res. FLUSH Reserved RX_EN SETUP EPC3 STALL Reserved EP_EN TXD2 TXFD TXS2 TX_URUN ACK_STAT TX_DONE TCOUNT IGN_ TXC2 TFWL FLUSH TOGGLE LAST TX_EN ISOMSK EPC4 STALL Reserved EP_EN RXD2 RXFD www.national.com...
  • Page 233 GMSKB GM[28:18] RTR IDE GM[17:15] GMSKX GM[14:0] XRTR BMSKB BM[28:18] RTR IDE BM[17:15] BMSKX BM[14:0] XRTR CIEN IEN[14:0] CIPND IPND[14:0] CICLR ICLR[14:0] CICEN ICEN[14:0] CSTPND Reserved NS[2:0] IST[3:0] CANEC REC[7:0] TEC[7:0] CEDIAG Res. MON CRC EBID[5:0] EFID[3:0] CTMR CTMR[15:0] www.national.com...
  • Page 234 Registers ADCA Device A Address Counter ADRA Device A Address ADCB Device B Address Counter ADRB Device B Address BLTC Block Length Counter BLTR Block Length DMACNTL Res. INCB INCA Res. OT DIR IND TCS DMASTAT Reserved OVR TC www.national.com...
  • Page 235 TMSEL Flash Program Memory Interface Registers FMIBAR Reserved FMIBDR FM0WER FM0WE FM1WER FM1WE FM2WER FM2WE FM3WER FM3WE IENP FMCTRL Reserved MER PER Res. CWD FMSTAT Reserved PERR EERR FULL BUSY FMPSR Reserved FTDIV FMSTART Reserved FTSTART FMTRAN Reserved FTTRAN www.national.com...
  • Page 236 FM3WE IENP FSMCTRL Reserved MER PER Res. CWD FSMSTAT Reserved FULL BUSY FSMPSR Reserved FTDIV FSMSTART Reserved FTSTART FSMTRAN Reserved FTTRAN FSMPROG Reserved FTPROG FSMPERASE Reserved FTPER FSMMERASE0 Reserved FTMER FSMEND Reserved FTEND FSMMEND Reserved FTMEND FSMRCV Reserved FTRCV www.national.com...
  • Page 237 CVSTAT Reserved CVOUTST CVINST CVF CVE TEST CVTEST Reserved _VAL CVRADD Reserved CVRADD CVRDAT CVRDAT CVDECOUT CVDECOUT CVENCIN CVENCIN CVENCPR CVENCPRT CLK3RES Registers CRCTRL Reserved ACE2 ACE1 PLLPWD FCLK SCLK PRSFC Reserved MODE FCDIV PRSSC SCDIV PRSAC ACDIV2 ACDIV1 www.national.com...
  • Page 238 Px Port High Drive Strength Enable PxALTS Px Pins Alternate Function Source Selection Registers ARSR ARSH ARSL ATSR ATSH ATSL ARFR ARFH ARFL ARDR0 ARDH ARDL ARDR1 ARDH ARDL ARDR2 ARDH ARDL ARDR3 ARDH ARDL ATFR ATFH ATFL ATDR0 ATDH ATDL www.national.com...
  • Page 239 URBF UTBE UnSTAT Reserved UXMIP URB9 UBKD UERR UDOE UnFRS Reserved UPEN UPSEL UXB9 USTP UCHAR UnMDSL1 URTS UFCE UERD UETD UCKS UBRK UATN UMOD UnBAUD UDIV7:0 UnPSR UPSC UDIV10:8 UnOVR Reserved UOVSR UnMDSL2 Reserved USMD UnSPOS Reserved USAMP www.national.com...
  • Page 240 TCRA TCRB TCRB TCNT2 TCNT2 TPRSC Reserved Reserved CLKPS TCKC Reserved Reserved C2CSEL C1CSEL TCTRL Reserved TAOUT TBEN TAEN TBEDG TAEDG TMDSEL TICTL Reserved TDIEN TCIEN TBIEN TAIEN TDPND TCPND TBPND TAPND TICLR Reserved Reserved TDCLR TCCLR TBCLR TACLR www.national.com...
  • Page 241 INTEN Res. NREF_CFG PREF_CFG TOUCH_CFG MUX_CFG DIFF ADCIN CLKEN OUTEN CLK- ADCACR CNVT TRG PRM Reserved CLKDIV ADCCNTRL Reserved AUTO EXT POL ADCSTART Write any value. ADCSCDLY ADC_DIV ADC_DELAY1 ADC_DELAY2 ADC_ ADC_ PEN_ ADCRESLT SIGN ADC_RESULT DONE OFLW DOWN www.national.com...
  • Page 242 Registers RNGCST Reserved IMSK Reserved DVALID RNGE RNGD RNGD RNGDIVH Reserved RNGDIV17:16 RNGDIVL RNGDIV15:0 www.national.com...

  • Page 243: Electrical Characteristics

    Total current into IOVCC pins 200 mA Total current into VCC pins (source) 200 mA If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distribu- Total current out of GND pins (sink) 200 mA tors for availability and specifications. Latch-up immunity ±200 mA...
  • Page 244 Running from internal memory (RAM), Iout = 0 mA, XCKI1 = 12 MHz, PLL disabled, X2CKI = 32.768 kHz, device put in power-save mode, Slow Clock derived from XCKI1 e. Iout = 0 mA, XCKI1 = Vcc, X2CKI = 32.768 kHz f. Halt current approximately doubles for every 20°C. www.national.com...

  • Page 245: Usb Transceiver Electrical Characteristics

    Total Capacitance of ADC Input ADCIN Switched Capacitance of ADC Input ADCINS Resistance of ADC Input Path kohm ADCIN Total Capacitance of ADC Reference Input ADCIN Switched Capacitance of ADC Reference Input ADCINS Resistance of ADC Reference Input Path kohm ADCIN www.national.com...

  • Page 246: Flash Memory On-Chip Programming

    FMPSR or FSMPSR register, and FTRCV is the contents of the FMRCV or FSMRCV register i. Cumulative program high voltage period for each row after erase t is the accumulated duration a flash cell is exposed to the programming voltage after the last erase cycle. www.national.com...

  • Page 247: Output Signal Levels

    Only when operating with an external square wave on X2CKI; otherwise a 32 kHz crystal network must be used between X2CKI and X2CKO. If Slow Clock is internally generated from Main Clock, it may not exceed this given limit. www.national.com...
  • Page 248 X1CKI X2CKI DS095 Figure 110. Clock Timing DS096 Figure 111. NMI Signal Timing RESET DS097 Figure 112. Non-Power-On Reset 0.9 VCC 0.1 VCC DS115 Figure 113. Power-On Reset www.national.com...

  • Page 249: Uart Timing

    After RE on CLK RXD (asynchronous mode) UART Output Signals TXD output valid (all signals with After RE on CLK COv1 propagation delay from CLK RE) TXD output valid After RE on CLK COv1 COv1 DS098 Figure 114. UART Asynchronous Mode Timing www.national.com...

  • Page 250: I/O Port Timing

    After RE on System Clock I/O Port Output Signals Output Valid Time After RE on System Clock COv1 Output Floating Time After RE on System Clock PORTS B, C (input) PORTS B, C (output) COv1 COv1 DS100 Figure 115. I/O Port Timing www.national.com...

  • Page 251: Advanced Audio Interface (Aai) Timing

    Frame Sync Valid High FSVH on SRFS/SFS 116, RE on SRCLK/SCK to FE Frame Sync Valid Low FSVL on SRFS/SFS 117, Transmit Data Valid RE on SCK to STD Valid SRCLK SRFS FSVH FSVL DS116 Figure 116. Receive Timing, Short Frame Sync www.national.com...
  • Page 252 DS117 Figure 117. Transmit Timing, Short Frame Sync SRCLK SRFS FSVH FSVL DS118 Figure 118. Receive Timing, Long Frame Sync DS119 Figure 119. Transmit Timing, Long Frame Sync www.national.com...

  • Page 253: Microwire/Spi Timing

    0.5 t 1.5 t MSKd only) Microwire Data Float After RE on MWCS MDOf (slave only) Normal Mode: After FE Microwire Data Out Hold MDOh Alternate Mode: After RE Microwire Data No Float (slave only) After FE on MWCS MDOnf www.national.com...
  • Page 254 (slave only) clocking modes of the Microwire MSKp MSKh MSKl MSKs MSKhd Data In MDls MDlh MDIDO (slave) MDOf MDOv MDOff MDOh MDODI (master) MSKd (slave) MCSs MCSh DS101 Figure 120. Microwire Transaction Timing, Normal Mode, SCIDL = 0 www.national.com...
  • Page 255 MSKp MSKh MSKh MSKhd MSKs Data In MDls MDlh MDIDO (slave) MDOf MDOv MDOf MDOh MDODO (master) (slave) MCSs MCSh DS102 Figure 121. Microwire Transaction Timing, Normal Mode, SCIDL = 1 www.national.com...
  • Page 256 MSKp MSKhd MSKs MSKh MSKl Data In MDls MDlh MDIDO (slave) MDOf MDOv MDOf MDOh MDODO (master) (slave) DS103 MCSs MCSh Figure 122. Microwire Transaction Timing, Alternate Mode, SCIDL = 0 www.national.com...
  • Page 257 Dl msb Dl lsb (slave) MDls MDlh MITOp MITOp MDIDO DO msb DO lsb (slave) MDOnf MDOf DS105 MCSs MCSh Figure 124. Microwire Transaction Timing, Data Echoed to Output, Normal Mode, SCIDL = 0, ECHO = 1, Slave Mode www.national.com...

  • Page 258: Access.bus Timing

    ) -1 SCLhigh SDA signal Fall time SDAfo SDA signal Rise time SDAro SDA hold time After SCL F.E. (7 × t ) - t SDAho SCLfo SDA valid time After SCL F.E. (7 × t ) + t SDAvo www.national.com...
  • Page 259 Figure 126. ACB Start and Stop Condition Timing Start Condition CSTRs CSTRh DHCs Note: In the timing tables the parameter name is added with an "o" for output signal timing and "i" for input signal timing. DS108 Figure 127. ACB Start Condition Timing www.national.com...
  • Page 260 SDAh CSLlow SCLhigh Note: In the timing tables the parameter name is added with an "o" for output signal timing and "i" for input signal timing. unless the parameter already includes the suffix. DS109 Figure 128. ACB Data Timing www.national.com...

  • Page 261: Usb Port Ac Characteristics

    Reference Min (ns) Max (ns) TA High Time Rising Edge (RE) on CLK TA Low Time RE on CLK TB High Time RE on CLK TB Low Time RE on CLK TA/TB DS169 Figure 129. Multi-Function Timer Input Timing www.national.com...

  • Page 262: Versatile Timing Unit (Vtu) Timing

    TIOx Input High Time 1.5 × T + 5ns Rising Edge (RE) on CLK TIOH TIOx Input Low Time 1.5 × T + 5ns RE on CLK TIOL TIOL TIOH TIOx DS110 Figure 130. Versatile Timing Unit Input Timing www.national.com...

  • Page 263: External Bus Timing

    Leading Edge (LE) Minimum Delay Time From SELx TE to SELy LE Output Hold Time 131, A[22:0] 132, D[15:0] 133, After RE on CLK 134, SEL[2:0] SELIO 131, Output Hold Time After RE on CLK 0.5 Tclk - 3 WR[1:0] www.national.com...
  • Page 264 Normal Read Early Write Normal Read Bus State A[21:0] A22 ('13 only) SELx SELy (y ≠ x) D[15:0] WR[1:0] DS124 Figure 131. Early Write Between Normal Read Cycles (No Wait States) www.national.com...
  • Page 265 Normal Read Late Write Normal Read Bus State A[21:0] A22 ('13 only) SELx (y ≠ x) SELy (y ≠ x) D[15:0] WR[1:0] DS125 Figure 132. Late Write Between Normal Read Cycles (No Wait States) www.national.com...
  • Page 266 Normal Read Normal Read Bus State A[21:0] A22 ('13 only) SELx (y ≠ x) SELy (y ≠ x) D[15:0] WR[1:0] DS126 Figure 133. Consecutive Normal Read Cycles (Burst, No Wait States) www.national.com...
  • Page 267 Bus State A21:0 A22 ('13 only) SELn, SELIO D[15:0] WR[1:0] DS127 Figure 134. Normal Read Cycle (Wait Cycle Followed by Hold Cycle) www.national.com...
  • Page 268 Fast Read Early Write Fast Read Bus State T1-2 T1-2 idle A[21:0] A22 ('13 only) SELx (y ≠ x) SELy (y ≠ x) D[15:0] WR[1:0] DS128 Figure 135. Early Write Between Fast Read Cycles www.national.com...

  • Page 269: Pin Assignments

    25, 32, 55, 78, 84, 113 4, 10, 17, 43, 45, 49, 53, IOGND 67, 76, 79, 110, 117, 119, 124 7, 13, 21, 42, 44, 47, 51, IOVCC 58, 74, 75, 80, 107, 115, 121, 127 X1CKO X1CKI BBCLK AGND www.national.com...
  • Page 270 RESET RFDATA ADC0 TSX+ I/O/HIZ 20mA+ ADC1 TSY+ I/O/HIZ 20mA+ ADC2 TSX- I/O/HIZ 20mA+ ADC3 TSY- I/O/HIZ 20mA+ ADC4 MUXOUT0 ADC5 MUXOUT1 ADC6 ADC7 ADCIN VREFP GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO www.national.com...
  • Page 271 Note 1: The ENV0, ENV1, ENV2, RESET, TCK, TDI, and TMS pins each have a weak pull-up to keep the input from floating. Note 2: These functions are always enabled, due to the direct low-impedance path to these pins. www.national.com...

  • Page 272: Lqfp-144 Package

    PH6/CANRX/WUI17 PF1/MDIDO/TIO2 PH5/TXD3/WUI16 IOVCC IOGND PF2/MDODI/TIO3 CP3BT26 (LQFP-144) PH4/RXD3/WUI15 IOGND IOVCC PH3/TXD2/WUI14 IOGND PG2/BTSEQ1/SRCLK PH2/RXD2/WUI13 PE5/SRFS/NMI PH1/TXD1/WUI12 PF4/SCK/TIO5 IOGND PF5/SFS/TIO6 PF6/STD/TIO7 IOVCC PF7/SRD/TIO8 IOGND IOVCC IOVCC PG7/BTSEQ3/TA PJ0/WUI18 PE4/CKX/TB DS182 Figure 137. CP3BT26 in the LQFP-144 Package (Top View) www.national.com...
  • Page 273 X1CKO X2CKI X2CKO ENV2 SLOWCLK ENV1 CPUCLK ENV0 PLLCLK RESET RFDATA ADC0 TSX+ I/O/HIZ 20mA+ ADC1 TSY+ I/O/HIZ 20mA+ ADC2 TSX- I/O/HIZ 20mA+ ADC3 TSY- I/O/HIZ 20mA+ ADC4 MUXOUT0 ADC5 MUXOUT1 ADC6 ADC7 ADCIN VREFP GPIO GPIO GPIO GPIO www.national.com...
  • Page 274 GPIO STD/TIO7 GPIO SRD/TIO8 GPIO RFSYNC GPIO RFCE GPIO SRCLK GPIO SCLK GPIO SDAT GPIO GPIO WUI10 GPIO GPIO RXD1/WUI11 GPIO TXD1/WUI12 GPIO RXD2/WUI13 GPIO TXD2/WUI14 GPIO RXD3/WUI15 GPIO TXD3/WUI16 GPIO CANRX/WUI17 GPIO CANTX GPIO WUI18 GPIO ASYNC GPIO www.national.com...
  • Page 275 Note 1: The ENV0, ENV1, ENV2, RESET, TCK, TDI, and TMS pins each have a weak pull-up to keep the input from floating. Note 2: These functions are always enabled, due to the direct low-impedance path to these pins. www.national.com...

  • Page 276: Revision History

    Changed LMX5251 interface circuit. Updated DC specifications for clock input 3/16/04 low voltage, reset input high voltage, and halt current. 5/10/04 Corrected NSIDs for no-lead solder parts. Moved revision history in front of physical 5/12/04 dimensions. Changed back page disclaimers. www.national.com...

  • Page 277: Physical Dimensions

    33.0 Physical Dimensions (millimeters) unless otherwise noted Figure 138. LQFP-128 Package Figure 139. LQFP-144 Package www.national.com...
  • Page 278 +33 (0) 1 41 91 8790 National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.

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