Operation Of Asynchronous Transfer - Epson S1C63558 Technical Manual

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Serial Interface)

4.11.7 Operation of asynchronous transfer

Asynchronous transfer is a mode that transfers by adding a start bit and a stop bit to the front and the
back of each piece of serial converted data. In this mode, there is no need to use a clock that is fully
synchronized clock on the transmit side and the receive side, but rather transmission is done while
adopting the synchronization at the start/stop bits that have attached before and after each piece of data.
The RS-232C interface functions can be easily realized by selecting this transfer mode.
This interface has separate transmit and receive shift registers and is designed to permit full duplex
transmission to be done simultaneously for transmitting and receiving.
For transfer data in the 7-bit asynchronous mode, either 7 bits data (no parity) or 7 bits data + parity bit
can be selected. In the 8-bit asynchronous mode, either 8 bits data (no parity) or 8 bits data + parity bit
can be selected.
Parity can be even or odd, and parity checking of received data and adding a party bit to transmitting
data will be done automatically. Thereafter, it is not necessary to be conscious of parity itself in the
program.
The start bit and stop bit are respectively fixed at one bit and data is transmitted and received by placing
the LSB (bit 0) at the front.
Fig. 4.11.7.1 Transfer data configuration for asynchronous system
Here following, we will explain the control sequence and operation for initialization and transmitting /
receiving in case of asynchronous data transfer. See "4.11.8 Interrupt function" for the serial interface
interrupts.
Initialization of serial interface
The below initialization must be done in cases of asynchronous system transfer.
(1) Setting of transmitting/receiving disable
To set the serial interface into a status in which both transmitting and receiving are disabled, "0"
must be written to both the transmit enable register TXEN and the receive enable register RXEN.
Fix these two registers to a disable status until data transfer actually begins.
(2) Port selection
Because serial interface input/output terminals SIN and SOUT are set as I/O port terminals P10
and P11 at initial reset, "1" must be written to the serial interface enable register ESIF in order to set
these terminals for serial interface use.
SCLK and SRDY terminals set in the clock synchronous mode are not used in the asynchronous
mode. These terminals function as I/O port terminals P12 and P13.
(3) Setting of transfer mode
Select the asynchronous mode by writing the data as indicated below to the two bits of the mode
selection registers SMD0 and SMD1.
7-bit mode: SMD0 = "0", SMD1 = "1"
8-bit mode: SMD0 = "1", SMD1 = "1"
86
Sampling
clock
7bit data s1 D0 D1 D2 D3 D4 D5 D6
7bit data
s1 D0 D1 D2 D3 D4 D5 D6 p
+parity
s1 D0 D1 D2 D3 D4 D5 D6 D7
8bit data
8bit data
s1 D0 D1 D2 D3 D4 D5 D6 D7
+parity
s1 : Start bit (Low level, 1 bit)
s2 : Stop bit (High level, 1 bit)
p : Parity bit
s2
EPSON
s2
s2
p s2
S1C63558 TECHNICAL MANUAL