Interrupt Factor - Epson S1C63558 Technical Manual

4.16.1 Interrupt factor

Table 4.16.1.1 shows the factors for generating interrupt requests.
The interrupt flags are set to "1" depending on the corresponding interrupt factors.
The CPU operation is interrupted when an interrupt factor flag is set to "1" if the following conditions are
established.
• The corresponding mask register is "1" (enabled)
• The interrupt flag is "1" (EI)
The interrupt factor flag is reset to "0" when "1" is written.
At initial reset, the interrupt factor flags are reset to "0".
Since the watchdog timer's interrupt is NMI, the interrupt is generated regardless of the setting above,
and no interrupt factor flag is provided.
Dialer (dialing cycle completion)
Ring detection (falling edge or rising edge)
Carrier detection (falling edge or rising edge)
Programmable timer 1 (counter = 0)
Programmable timer 0 (counter = 0)
Serial interface (1) (receive error)
Serial interface (1) (receive completion)
Serial interface (1) (transmit completion)
Serial interface (2) (receive error)
Serial interface (2) (receive completion)
Serial interface (2) (transmit completion)
K00–K03 input (falling edge or rising edge)
K10–K13 input (falling edge or rising edge)
Clock timer 1 Hz (falling edge)
Clock timer 2 Hz (falling edge)
Clock timer 8 Hz (falling edge)
Clock timer 32 Hz (falling edge)
Stopwatch timer (1 Hz)
Stopwatch timer (10 Hz)
Note: After an interrupt occurs, the same interrupt will occur again if the interrupt enabled state (I flag =
"1") is set or the RETI instruction is executed unless the interrupt factor flag is reset. Therefore, be
sure to reset (write "1" to) the interrupt factor flag in the interrupt service routine before shifting to
the interrupt enabled state.
S1C63558 TECHNICAL MANUAL
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Interrupt and HALT)
Table 4.16.1.1 Interrupt factors
Interrupt factor
EPSON
Interrupt factor flag
( FFF9H•D0 )
ID
( FFFAH•D0 )
IRDET
( FFFAH•D1 )
ICDET
( FFF2H•D1 )
IPT1
( FFF2H•D0 )
IPT0
( FFF3H•D2 )
ISER
( FFF3H•D0 )
ISRC
( FFF3H•D1 )
ISTR
( FFF8H•D2 )
ISERS
( FFF8H•D0 )
ISRCS
( FFF8H•D1 )
ISTRS
( FFF4H•D0 )
IK0
( FFF5H•D0 )
IK1
( FFF6H•D3 )
IT3
( FFF6H•D2 )
IT2
( FFF6H•D1 )
IT1
( FFF6H•D0 )
IT0
( FFF7H•D1 )
ISW1
( FFF7H•D0 )
ISW10
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