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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Serial Interface)
RXEN: Serial interface (1) receive enable register (FF72H•D2)
RXENS: Serial interface (2) receive enable register (FF5AH•D2)
Sets the serial interface to the receive enabled status.
When "1" is written: Receive enabled
When "0" is written: Receive disabled
Reading: Valid
When "1" is written to RXEN/RXENS, the serial interface shifts to the receive enabled status and shifts to
the receive disabled status when "0" is written.
Set RXEN/RXENS to "0" when making the initial settings of the serial interface and similar operations.
At initial reset, this register is set to "0".
RXTRG: Serial interface (1) receive trigger/status (FF72H•D3)
RXTRGS: Serial interface (2) receive trigger/status (FF5AH•D3)
Functions as the receive start trigger or preparation for the following data receiving and the operation
status indicator (during receiving/during stop).
When "1" is read: During receiving
When "0" is read: During stop
When "1" is written: Start receiving/following data receiving preparation
When "0" is written: Invalid
RXTRG/RXTRGS has a slightly different operation in the clock synchronous system and the asynchronous
system.
The RXTRG/RXTRGS in the clock synchronous system is used as the trigger for starting receive opera-
tion.
Write "1" into RXTRG/RXTRGS to start receiving at the point where the receive data has been read and
the
following receive preparation has been done. (In the slave mode, SRDY becomes "0" at the point where
"1" has been written into into the RXTRG/RXTRGS.)
In the asynchronous system, RXTRG/RXTRGS is used for preparation of the following data receiving.
Read the received data located in the receive data buffer and write "1" into RXTRG/RXTRGS to inform
that the receive data buffer has shifted to empty. When "1" has not been written to RXTRG/RXTRGS, the
overrun error flag OER is set to "1" at the point where the following receiving has been completed. (When
the receiving has been completed between the operation to read the received data and the operation to
write "1" into RXTRG/RXTRGS, an overrun error occurs.)
In addition, RXTRG/RXTRGS can be read as the status. In either clock synchronous mode or asynchro-
nous mode, when RXTRG/RXTRGS is set to "1", it indicates receiving operation and when set to "0", it
indicates that receiving has stopped.
At initial reset, RXTRG/RXTRGS is set to "0".
TRXD0–TRXD7: Serial interface (1) transmit/receive data (FF74H, FF75H)
TRXD0S–TRXD7S: Serial interface (2) transmit/receive data (FF5CH, FF5DH)
During transmitting
Transmitting data is set.
When "1" is written: High level
When "0" is written: Low level
Write the transmitting data prior to starting transmition.
In the case of continuous transmitting, wait for the transmit completion interrupt, then write the data.
The TRXD7/TRXD7S becomes invalid for the 7-bit asynchronous mode.
Converted serial data for which the bits set at "1" as High (V
Low (V
) level are output from the SOUT terminal.
SS
96
) level and for which the bits set at "0" as
DD
EPSON
S1C63558 TECHNICAL MANUAL
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