Serial Interface (1), (2) Ac Characteristics - Epson S1C63558 Technical Manual

CHAPTER 7: ELECTRICAL CHARACTERISTICS

7.6 Serial Interface (1), (2) AC Characteristics

1. Clock synchronous master mode (during 1 MHz operation)
Condition: V
=3.0V, V
DD SS
Item
Transmitting data output delay time
Receiving data input set-up time
Receiving data input hold time
Note that the maximum clock frequency is limited to 1 MHz.
2. Clock synchronous slave mode (during 1 MHz operation)
Condition: V
=3.0V, V
DD SS
Item
Transmitting data output delay time
Receiving data input set-up time
Receiving data input hold time
Note that the maximum clock frequency is limited to 1 MHz.
<Master mode>
SCLK OUT
SOUT
SIN
<Slave mode>
SCLK IN
SOUT
SIN
3. Asynchronous system
Condition: V
=2.2 to 5.5V, V
DD
Item
Start bit detection error time 1
Erroneous start bit detection range time 2
1 Start bit detection error time is a logical delay time from inputting the start bit until internal sampling begins operating.
(Time as far as AC is excluded.)
2 Erroneous start bit detection range time is a logical range to detect whether a LOW level (start bit) has been input again
after a start bit has been detected and the internal sampling clock has started. When a HIGH level is detected, the start bit
detection circuit is reset and goes into a wait status until the next start bit. (Time as far as AC is excluded.)
SIN
Sampling
clock
Erroneous
start bit
detection signal
164
=0V, Ta=-20 to 70 C, V =0.8V
IH1
Symbol
t
smd
t
sms
t
smh
=0V, Ta=-20 to 70 C, V =0.8V
IH1
Symbol
t
ssd
t
sss
t
ssh
V
OH
V
OL
t
smd
V
OH
V
OL
t
sms
V
IH1
V
IL1
V
IH1
V
IL1
t
ssd
V
OH
V
OL
t
sss
V
IH1
V
IL1
=0V, Ta=-20 to 70 C
SS
Symbol
t
sa
1
t
sa
2
Start bit
t
sa
1
t
sa
, V =0.2V , V =0.8V
DD IL1 DD OH
Min.
400
200
, V =0.2V , V =0.8V
DD IL1 DD OH
Min.
400
200
t
smh
t
ssh
Min.
0
t
9 /16
t
2
EPSON
, V =0.2V
DD OL DD
Typ. Max.
200
, V =0.2V
DD OL DD
Typ. Max.
500
Typ. Max.
t
/16
t
10 /16
Stop bit
S1C63558 TECHNICAL MANUAL
Unit
ns
ns
ns
Unit
ns
ns
ns
Unit
s
s