Epson S1C63558 Technical Manual page 55

Register
Address
D3 D2
IOC33 IOC32 IOC31
FF4CH
R/W
PUL33 PUL32 PUL31
FF4DH
R/W
P33 P32
(XSRDYS) (XSCLKS) (SOUTS)
FF4EH
R/W
0 SMD1S SMD0S ESIFS
FF58H
R
EXLCDC ALOFF ALON
FF61H
R/W
0 SMD1 SMD0
FF70H
R
*1 Initial value at initial reset
*2 Not set in the circuit
*3 Constantly "0" when being read
(1) Selection of port function
EXLCDC: Expanded LCD driver signal control register (FF61H•D3)
Sets P22 and P23 to the CL signal and the FR signal output ports.
When "1" is written: CL/FR signal output
When "0" is written: I/O port
Reading: Valid
When setting P22 to the CL (LCD synchronous signal) output and P23 to the FR (LCD frame signal)
output, write "1" to this register and when they are used as I/O ports, write "0".
The CL and FR signals are output from the P22 terminal and P23 terminal immediately after the functions
are switched by the EXLCDC register. In this case, the control registers for P22 and P23 can be used as
general purpose registers that do not affect the output.
At initial reset, this register is set to "0".
S1C63558 TECHNICAL MANUAL
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (I/O Ports)
Table 4.6.6.1(b) Control bits of I/O ports
D1 D0 Name Init 1
IOC33 0
IOC30
IOC32 0
IOC31 0
IOC30 0
PUL33 1
PUL30 PUL32 1
PUL31 1
PUL30 1
P33 – 2
P31 P30
(SINS)
P32 – 2
P31 – 2
2
P30 –
3 2
0 –
SMD1S 0
SMD0S 0
R/W
ESIFS 0
EXLCDC 0
LPAGE
ALOFF 1
ALON 0
LPAGE 0
0 3 – 2
ESIF
SMD1 0
SMD0 0
R/W
ESIF 0
1 0
Output Input P33 I/O control register
General-purpose register when SIF (clock sync. slave) is selected
Output Input P32 I/O control register
General-purpose register when SIF (clock sync.) is selected
Output Input P31 I/O control register (ESIFS=0)
General-purpose register when SIF is selected
Output Input
P30 I/O control register (ESIFS=0)
General-purpose register when SIF is selected
On Off
P33 pull-up control register
General-purpose register when SIF (clock sync. slave) is selected
On Off
P32 pull-up control register
General-purpose register when SIF (clock sync. master) is selected
SCLK (I) pull-up control register
when SIF (clock sync. slave) is selected
On Off P31 pull-up control register (ESIFS=0)
General-purpose register when SIF is selected
On Off P30 pull-up control register (ESIFS=0)
SIN pull-up control register when SIF is selected
High Low
P33 I/O port data
General-purpose register when SIF (clock sync. slave) is selected
High Low
P32 I/O port data
General-purpose register when SIF (clock sync.) is selected
High Low
P31 I/O port data (ESIFS=0)
General-purpose register when SIF is selected
High Low P30 I/O port data (ESIFS=0)
General-purpose register when SIF is selected
Unused
Serial I/F (2)
mode selection
SIF I/O Serial I/F (2) enable (P3x port function selection)
Enable Disable
Expanded LCD driver signal control
All Off Normal LCD all Off control
All On Normal
LCD all On control
F100-F15F F000-F05F Display memory area selection (when 1/8 duty is selected)
General-purpose register when 1/16, 1/17 duty is selected
Unused
Serial I/F (1)
mode selection
SIF I/O Serial I/F (1) enable (P1x port function selection)
EPSON
Comment
[SMD1S, 0S] 0
Mode Clk-sync. master Clk-sync. slave
[SMD1S, 0S] 2
Mode Async. 7-bit Async. 8-bit
[SMD1, 0] 0
Mode Clk-sync. master Clk-sync. slave
[SMD1, 0] 2
Mode Async. 7-bit Async. 8-bit
1
3
1
3
45