Core 2 duo mobile processor, intel core 2 solo mobile processor and intel core 2 extreme mobile processor on 45-nm process, platforms based on mobile intel 4 series express chipset family (113 pages)
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Coffee Lake S Reference Validation Platform (RVP) Customer Reference Board (CRB) User Guide Revision 2.0 May 2018 Intel Confidential Document Number: 572913...
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All information provided here is subject to change without notice. Contact your Intel representative to obtain the latest Intel product specifications and roadmaps.
Rework to Enable Vertical USB Port ........... 43 8.2.2 Rework to Enable TTK Glider Card in eSPI Mode ......46 8.2.3 Rework to Enable CNVi Module ..........50 8.2.4 Rework to Enable PCH XDP ............52 Intel Confidential User Guide...
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Rework to Enable Higher Current Profile on Front Panel USB-C Titan Ridge AIC ................93 8.4.2 Rework to Enable Sx Wake on Front Panel USB-C Titan Ridge AIC . 94 8.4.3 Rework to Enable RTD3 Flow on Front Panel USBC Titan Ridge AIC 95 Intel Confidential User Guide...
Universal Serial Bus Video Graphics Array Voltage Regulator Embedded Controller Extended Debug Port Reference Documents Document Title CCL# Coffee Lake S Platform UDIMM RVP Technical Documentation Kit 571506 Coffee Lake S CNP Platform Design Guide 571264 §§ Intel Confidential User Guide...
CFL-S RVP Features CFL-S RVP Features CFL RVP Block Diagram Refer to the below figure for Coffee Lake H DDR4 RVP block diagram. Figure 1. Coffee Lake S DDR4 RVP Block Diagram (Shown UDIMM Only) Intel Confidential User Guide...
2x legacy vertical SATA cable connector (default) 1x M.2 SSD, x4 PCIe* or x1 SATA, Socket 3 Key M (default) ZPODD Connectivity WLAN M.2 Socket 1 Hybrid Key E for discrete or CNVi GBE LAN Jacksonville Thunderbolt™ Through AIC Intel Confidential User Guide...
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3.3V and 1.8V Embedded Controller eSPI based EC device down only. Power Delivery Discrete iMVP8 VR with ATX Power supply USB Power Delivery - Provider Over Type-C only connectors with 5V@3A profile OS Support Windows*, Chrome*, Linux*. §§ Intel Confidential User Guide...
The CNP-H chipset is the primary clock generator for all sub-system and CPU clocks on the CFL-S RVP. All the sub-system clocks and external clock outputs are derived through internal PLLs. A high level block diagram of the chipset clock interface is given below Intel Confidential User Guide...
• The processor supports only 3 streaming independent and simultaneous display combinations of DP/eDP/HDMI/DVI monitors. • DDI ports can be configured either as Display port or HDMI port. • HDMI2.0 support is via External LS-PCON chip from Megachips – MDCP2800. Intel Confidential User Guide...
USB 2 Port Mapping CFL-S RVP USB 2.0 Port # USB2.0 Allocation Discrete USB Type C FP #1 USB3.1 Type A BP #2 Type C connector BP #1 USB3.1 Type A FP #1 USB3.1 Type A FP #2 Intel Confidential User Guide...
Figure 7. USB-3 Mapping USB Type-C Support 1x discrete Type-C on Front panel: • Based out of PD controller and TUSB1046 active switch which are soldered on the RVP and terminated to a front panel header. Intel Confidential User Guide...
Memory, 1X3 header, Option to PSS, PCIe* SMBUS DT Slots, DAC for AVMC, FRU, LPC TPM header, CPU XDP SMLINK0(muxed with I2C2 and ISH UART0) LAN, NFC SMLINK1 SMLINK2 Used as GPIOs SMLINK3 Used as GPIOs SMLINK4 Used as GPIOs Intel Confidential User Guide...
All PCIe* are populated − − All VR rail is under Imax Suggested power supply − • EA-550 PLATINUM (Validated by Intel PRE) • CPU Voltage Rails − IMVP8 Using Intersil* ISL95856 Core, GT only support 0V VBoot. − Core is a 4-Phase VR and GT is a 2-Phase VR.
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5V or 9V, 3A Type-C VR. − 1.2 for LSPCON supply − − CNVi rail margin VRs. Used on PnP board only • Voltage Rails with SMBUS Margin Capability − VCCSA VCCSFR_OC − VCCIO − − VDDQ §§ Intel Confidential User Guide...
Hardware Assembly Instructions Hardware Assembly Instructions CFL CPU Hardware Assembly Instructions CFL-S CPU that comes in 1151 LGA package over the H4 socket soldered down on RVP. Intel Confidential User Guide...
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3. Close the lid and hook the lever below the lid. 4. Mount the heatsink (Off-The-Shelf heatsink not supplied with RVP). • Off the shelf LGA Heatsink • Supplied with Pre-Applied Thermal Grease • 65W Heat Sink with IPN: E97379-001 Intel Confidential User Guide...
3 in-lb using the torque wrench and 2mm hex head. e. Ensure that the semicircular cutout in the stiffener plates is oriented in the same direction as the chamfer on the socket and Pin 1 on the board. Intel Confidential User Guide...
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Pin 1 direction of all previously installed components. Past this point, failing to line up all of the Pin 1 features in the assembly may − cause irreversible damage to the package and socket. Intel Confidential User Guide...
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It is difficult or impossible to install the lid with the heatsink screw threaded too far down. Place the lid on top of the stiffener plate, slipping the shoulder screws through the four keyholes and turning the lid clockwise slightly to lock it in place. Intel Confidential User Guide...
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Hardware Assembly Instructions STEP 4 – Torque the Heatsink Screw a. Using the 4mm hex driver for the torque wrench, tighten the heatsink screw to 6 in-lb. Intel Confidential User Guide...
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Hardware Assembly Instructions §§ Intel Confidential User Guide...
Insert DDR4 UDIMM modules into UDIMM connectors (RefDes: J1E5, J1F2, J1F3, J1F4). Step3: Verify presence of RTC coin cell in Battery Holder (RefDes: XBT9C1). Step4: Insert hard disk drive in cable connect (RefDes: J6H2 or J6H1) or PCIe*/SATA based SSD in M.2 socket 3 (RefDes: J8H1). Intel Confidential User Guide...
Step9: As the system boots, press F2 to enter the BIOS setup screen. Check time, date, and configuration settings. The default settings should be sufficient for most users with the exception of Intel ® Speed Step Technology. This feature is disabled by default and can be enabled in setup.
5. Load File: After blank check operation is completed without problem, click File button. Find and open the file. If the suffix of your image is .rom, select the Data Format: ROM. If the suffix is .bin, select Data Format: Raw Binary. Finally, click Ok button. Intel Confidential User Guide...
1.8V SUSACK pin in the PCH in eSPI mode causing board to be stuck at EC09 POSTCODE. This rework will disconnect the SUSACK path in eSPI mode. Impact of implementing the rework: Board will boot normally after this rework in eSPI mode Intel Confidential User Guide...
Rework to Enable Vertical USB Port Description: This rework is to enable the vertical USB port Impact of implementing the rework: Vertical USB will work. The USB back panel Port 6 will not work after this rework. Details: SMT Resistor rework. Intel Confidential User Guide...
Impact of implementing the rework: Default TR SP back panel would be enabled. After rework FP TR DP AIC would be enabled and BP TR SP will not work. Details: SMD Resistor/Capacitor rework Applicable To: H3AZ01, H3AZ02, H4BZ01, H3BZ02. Intel Confidential User Guide...
Rework to Keep USB Compliant on FP Discrete Type C Description: This rework is keep the USB PDG compliant with the active switch datasheet and Intel PDG. Impact of implementing the rework: The resistor on Tx lanes between PCH and type C active switch needs to be replaced with 0.1uf to keep it compliant with the...
BIAS Resistor PDG Compliance for 24MHz Clock Description: This rework is keep the 24MHz clock’s bias resistor compliant as per Impact of implementing the rework: The current 1MOhm resistor is to be replaced with 200kohm resistor Intel Confidential User Guide...
Reworks Figure 83. Schematic Snapshot Figure 84. Layout Snapshot – Top Layer AIC Reworks Note: Resistor THR99 is to be replaced with 0 Ohm, 5%, 0402. This is applicable to U17221, H6AZ03, H6AZ06, H7AZ01 AIC boards. Intel Confidential User Guide...
3.3V Dual pull up. Impact of implementing the rework: When trying to do Sx Wake with TBT device connected, CAT error/Device getting lost behavior is observed without this rework Details: SMD Resistor and blue wire rework. Intel Confidential User Guide...
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