Ide Interface Connectors - NEC IMAGE P100E Service Manual

IDE INTERFACE CONNECTORS

All signal levels in the IDE interface are TTL compatible. A logic 1 is a signal whose volt-
age level is between 2.0 and 5.0 V. A logic 0 is a signal measuring between 0.00 V and
0.70 V.
The two system board IDE connectors are physically identical. Both are fast PCI local bus
IDE connectors. Table Appendix B-10 provides the IDE pin assignments. All signals on
the Host interface have the prefix HOST. All negatively active signals are further prefixed
with a "–" designation. All positively active signals are prefixed with a "+" designation.
Table Appendix B-10 IDE Connector (J30/J32) Pin
Pin
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31*
33
35
37
39
*The PCI IDE connector uses IRQ15
Assignments
Signal
–HOST RESET
+HOST DATA 7
+HOST DATA 6
+HOST DATA 5
+HOST DATA 4
+HOST DATA 3
+HOST DATA 2
+HOST DATA 1
+HOST DATA 0
GND
DRQ3
–HOST IOW
–HOST IOR
IOCHRDY
–DACK3
+HOST IRQ14
+HOST ADDR 1
+HOST ADDR 0
–HOST CSO
–HOST SLV/ACT
Connector Pin Assignments
Pin Signal
2 GND
4 +HOST DATA 8
6 +HOST DATA 9
8 +HOST DATA 10
10 +HOST DATA 11
12 +HOST DATA 12
14 +HOST DATA 13
16 +HOST DATA 14
18 +HOST DATA 15
20 KEY
22 GND
24 GND
26 GND
28 +HOST ALE
30 GND
32 –HOST IO16
34 GND
36 +HOST ADDR 2
38 –HOST CS1
40 GND
B-9