Ide Interface Connectors; Table B-10 Ide/Pci Connector Pin Assignments - NEC DIRECTION L Service Manual

IDE INTERFACE CONNECTORS

All signal levels in the IDE interface are TTL compatible. A logic 1 is a signal whose
voltage level is between 2.0 and 5.0 V. A logic 0 is a signal measuring between 0.00 V and
0.70 V.
The two system board IDE connectors are physically identical. Electrically, the primary
IDE/PCI bus IDE connector is faster and the secondary IDE/PCI connector is slower.
Table B-10 provides the IDE pin assignments. All signals on the Host interface have the
prefix HOST. All negatively active signals are further prefixed with a "-" designation. All
positively active signals are prefixed with a "+" designation.

Table B-10 IDE/PCI Connector Pin Assignments

Pin Description
1 Reset IDE
3 Host data 7
5 Host data 6
7 Host data 5
9 Host data 4
11 Host data 3
13 Host data 2
15 Host data 1
17 Host data 0
19 Ground
21 DDRQ0 (DDRQ1)
23 I/O write#
25 I/O read#
27 IOCHRDY
29 DDACK# (DDACK1#)
31 IRQ 14 (IRQ 15)
33 Address 1
35 Address 0
37 Chip select 1P# (Chip select 1S#)
39 Activity#
Note: Signal names in parentheses ( ) are for the secondary IDE connector.
Connector Pin Assignments
Pin Description
2 Ground
4 Host data 8
6 Host data 9
8 Host data 10
10 Host data 11
12 Host data 12
14 Host data 13
16 Host data 14
18 Host data 15
20 Key
22 Ground
24 Ground
26 Ground
28 P_ALE (Cable select pullup)
30 Ground
32 Reserved
34 Reserved
36 Address 2
38 Chip select 3P# (Chipselect 3S#)
40 Ground
B-9