Ide Interface Connector; Ide/Pci Connector Pin Assignments - NEC Direction SP E-Series Reference Manual

IDE Interface Connector

All signal levels in the IDE interface are TTL compatible. A logic 1 is a signal
whose voltage level is between 2.0 and 5.0 V. A logic 0 is a signal measuring
between 0.00 and 0.70 V.
The two system board IDE connectors are physically identical. The following
table provides the IDE pin assignments. All signals on the Host interface have
the prefix HOST. All negatively active signals are further prefixed with a "-"
designation. All positively active signals are prefixed with a "+" designation.
Pin Description
1 Reset IDE
3 Data 7
5 Data 6
7 Data 5
9 Data 4
11 Data 3
13 Data 2
15 Data 1
17 Data 0
19 Ground
21 DDRQ0 (DDRQ1)
23 I/O write#
25 I/O read#
27 IOCHRDY
29 DDACK0# (DDACK1#)
31 IRQ 14 (IRQ 15)
33 Address 1
35 Address 0
37 Chip select 1P# (Chip select 1S#)
39 Activity#
Note: Signal names in parentheses () are for the secondary IDE connector.

IDE/PCI Connector Pin Assignments

Pin
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
Description
Ground
Data 8
Data 9
Data 10
Data 11
Data 12
Data 13
Data 14
Data 15
Key
Ground
Ground
Ground
P_ALE (Cable select pullup)
Ground
Reserved
Reserved
Address 2
Chip select 3P# (Chip select 3S#)
Ground
Connector Pin Assignments B-9