Power Supplies; Ad4080 Power Supply; Amplifier Power Supply; Conversion And Data Clock Generation Circuit - Analog Devices EVAL-AD4080-FMCZ User Manual

User Guide
EVALUATION BOARD HARDWARE GUIDE

POWER SUPPLIES

The EVAL-AD4080-FMCZ is designed to operate from a 12 V sup-
ply provided from the host controller board via the FMC connector.
The 12 V power supply is regulated down using a combination
of switching regulators and linear dropout (LDOs) regulators to
generate the necessary power rails for the on-board circuitry.
Figure 6. Power Circuitry Simplified Schematic

AD4080 POWER SUPPLY

The AD4080 requires three major power supplies:
VDD33: 3.3 V analog supply rail.
►
VDD11: 1.1 V ADC core supply.
►
IOVDD: 1.1 V digital interface supply.
►
The AD4080 includes integrated power supply decoupling;there-
fore, no external power supply decoupling was included on-board
for the AD4080 power supply rails.
The following can be configured in this circuit:
1.1 V rails (VDD11 and IOVDD) source
►
On-board generated rails (default): The rails are taken in from
►
the LT3045 regulators (U34 and U35), as shown in
Internal AD4080 LDO regulator: An LDO internal to the
►
AD4080 can be enabled and used to power both 1.1 V rails.
Refer to the AD4080 data sheet for more details pertaining to
the power supply rails and requirements.
Off-board external supply.
►
3.3 V rail source
►
On-board generated rail (default): The rail is supplied by an
►
LT3045 LDO regulator (U21), as shown in
Off-board external supply.
►
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AMPLIFIER POWER SUPPLY

The signal conditioning circuitry of the EVAL-AD4080-FMCZ was
designed to operate from +5 V and −5V rails. The positive and
negative rails of the U1 and U2 amplifiers are supplied from the +5
V VDDAFE rail and the −5 V VSSAFE rail.
The positive and negative rails of the fully differential U3 amplifier
and the optional third stage A1 and A2 amplifiers are supplied from
the +5 V VDDDRV rail and −5 V VSSDRV rail. The common-mode
buffer A5 amplifier is configured for a unipolar power supply; the
positive supply rail of A5 is provided from the +5 V VDDDRV rail,
and the negative supply rail is connected to ground.
CONVERSION AND DATA CLOCK
GENERATION CIRCUIT
The EVAL-AD4080-FMCZ contains the necessary circuits to gener-
ate low jitter data (CLK+ and CLK−) and conversion (CNV+ and
CNV−) clocks across the full operating range of the AD4080. This
low jitter circuitry allows processing with fidelity full-scale input
signals up to 4 MHz.
The circuit consists of a 25 MHz complementary metal–oxide
semiconductor (CMOS) reference oscillator (Y1), the
deband synthesizer, and the
in
oscillator and produces a higher frequency output with the frequen-
cy multiplication factor being programmable by the software. The
synthesizer output is then fed to the clock buffer, which generates
the clock (CLK+ and CLK−) and convert (CNV+ and CNV−) signals,
from which, it can apply separate programmable frequency division
factors. Therefore, the software sets the CLK and CNV signal
frequencies by programming the ADF4350 and AD9508 through
their serial interfaces. In practice, to change the sample rate, the
user changes the Sampling Frequency (MHz) field in the Board
Level view of the
The 25 MHz oscillator and synthesizer can be bypassed, and an
external data clock reference supplied instead (through the CLKIN
SMA connector) to the AD9508 to allow synchronization with an
Figure 6.
existing system clock solution. See the
Source
synthesizer circuits.
Figure 6.
Connectivity is established at the output of the AD9508 to optionally
generate a third output signal, a synchronous FPGA reference
AD9508
Figure 7. The synthesizer takes in the 25 MHz signal from the
ACE Software
section for details regarding bypassing the oscillator and
Figure 7. Simplified Diagram of the Clock Circuitry
EVAL-AD4080
ADF4350
clock fanout buffer as shown
as is detailed in Figure 10.
Using an External Clock
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