Digital Interface - Analog Devices EVAL-AD4080-FMCZ User Manual

User Guide EVAL-AD4080
EVALUATION BOARD HARDWARE GUIDE
clock (FPGACLK+ and FPGACLK−). However, this function is not
supported yet.
By default, the EVAL-AD4080-FMCZ conversion control is config-
ured to operate in LVDS mode; therefore, the AD9508 drives
the CNV+ and CNV− pins differentially. The hardware includes
provisions to allow using a single-ended CMOS signal instead, see
the Configuring for CMOS CNV Mode section for further details.

DIGITAL INTERFACE

The EVAL-AD4080-FMCZ utilizes the FMC connector (P3) from
the ZedBoard to support ADC device configuration via the 4-wire
SPI, conversion result access using the LVDS interface, and con-
version control in LVDS mode. The ZedBoard acts as the conduit
for communication between the ACE Software plug-in and the
EVAL-AD4080-FMCZ hardware.
The AD4080 operates with a 1.1 V digital interface supply voltage.
To translate between this 1.1 V level and the digital interface volt-
age level of the ZedBoard (VADJ), SN74AVC1T45DCKR bidirec-
tional level translators (U4, U5, U6, U7, U11, U12, U13, U14, U15,
U16, and U17) are used on the EVAL-AD4080-FMCZ hardware.
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