Power Supplies - Analog Devices EVAL-ADAQ7767-1 User Manual

User Guide
EVALUATION BOARD HARDWARE

POWER SUPPLIES

The EV-ADAQ7767-1FMC1Z obtains its power from the 3.3 V rail of
the SDP-H1 by default, which is boosted and regulated to provide
the supply rails required by the ADAQ7767-1, voltage reference,
additional signal conditioning, and the IEPE interface.
The ADAQ7767-1 contains an internal 5 V low dropout (LDO)
regulator with the purpose of simplifying the power solution and
layout of the signal chain µModule. Together with this internal LDO
regulator, the ADAQ7767-1 can operate with only a 5.3 V and 3.3
V rail. In the EV-ADAQ7767-1FMC1Z, the 3.3 V from the SDP-H1
directly powers the VDD_IO. This 3.3 V rail is boosted to 5.3 V
by the LTC3526LB-2, which is then regulated by the internal LDO
regulator to 5 V, powering VDD_FDA, VDD_ADC, VDD2_ADC, the
ADR444 reference voltage, and the
buffer. The 5.3 V LED (DS2) is on when a 5.3 V rail is powered by
the on-board or external 5.3 V supply.
The higher voltage rails used by the input buffers and the IEPE
interface, VDD/VSS_BUF and HV_VDD, are connected to the on-
board rails, INT_VDD and INT_VSS, which are powered by the
ADP5076 dual switching regulator,
tor, and ADP7182 negative LDO regulator, as shown in
This power tree boosts and regulates the 3.3 V to a default of +15
V and −15 V. For the larger input signal covered by the IN3 (28 V)
range, the buffers and IEPE interface may require a higher voltage
supply. In this case, the voltage of the rails can be increased to
28 V by moving the 0 Ω links at the feedback resistors of the
ADP5076, ADP7124, and ADP7182. As an option, VDD/VSS_BUF
and HV_VDD can also be connected to the external supply rails,
Table 2. Recommended Power Supply Rails when Using Input Buffers and/or An IEPE Interface
Input Range (V) ADAQ7767-1 Input Pins
±4.096 (Voltage Input to IN1+ and IN1−
AINP/AINN)
±4.096 (AC-Coupled IEPE IN1+ to IEPE_IN
Input to IEPE_IN)
IN1− to GND
±11.2 (Voltage Input to AINP/ IN2+ and IN2−
AINN)
±11.2 (AC-Coupled IEPE IN2+ to IEPE_IN
Input to IEPE_IN)
analog.com
ADA4807-1 optional reference
ADP7142 positive LDO regula-
Figure 8.
IEPE Supply HV_VDD
(V)
Not applicable
HV_VDD = EXT_VDD =
24
Not applicable
HV_VDD = EXT_VDD =
24
EVAL-ADAQ7767-1
EXT_VDD and EXT_VSS. See
supply rails when using the buffers and/or the IEPE interface and
Table 3 for the power supply link options.
Each supply is decoupled at the point where the supply enters
the EV-ADAQ7767-1FMC1Z and again at the point where the EV-
ADAQ7767-1FMC1Z connects to each device. The ADAQ7767-1
has built-in, 0.1 μF supply decoupling capacitors on the VDD_FDA,
VDD_ADC, VDD2_ADC, and VDD_IO supply pins.
The power solution for the EV-ADAQ7767-1FMC1Z was designed
with the aid of LTpowerCAD. This tool is helpful in planning and
designing power systems, with component recommendations to
optimize the overall power solution.
Figure 8. VDD_BUF, VSS_BUF, and HV_VDD Jumper Settings
Buffer Supply VDD_BUF (V)
Positive Negative
P_BST = 17 N_BST = −17
VDD_BUF = INT_VDD = VSS_BUF = INT_VSS =
15 −15
P_BST = 17 N_BST = −17
VDD_BUF = INT_VDD = VSS_BUF = INT_VSS =
15 −15
P_BST = 17, VDD_BUF N_BST = −17,
= INT_VDD = 15 VSS_BUF = INT_VSS =
−15
P_BST = 17 N_BST = −17
Table 2 for the recommended power
Comments
By default, buffers use on-
board supplies, INT_VDD
and INT_VSS, set at ±15V.
If input is from an IEPE
sensor applied to IEPE_IN
using this input range, AC-
coupled IEPE_IN to the
buffer by replacing R13
with a capacitor. Connect
HV_VDD to EXT_VDD and
externally supply EXT_VDD
with 24 V.
By default, buffers use on-
board supplies, INT_VDD
and INT_VSS, set at ±15 V.
If input is from an IEPE
sensor applied to IEPE_IN
using this input range, AC-
coupled IEPE_IN to the
buffer by replacing R13
with a capacitor. Connect
HV_VDD to EXT_VDD and
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