Trigger Amplifiers And Switching - Tektronix 2235A Instruction Manual

Theory of Operatlon
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2235A lnstructlon
TRIGGER AMPLIFIERS AND SWITCHING
TheTrigger Amplifiers, shown on Diagram 4, provide sig-
nals to the Trigger Generator circuit from either the Verti-
cal Preamplifiers, the EXT INPUTconnector, or the power
line. The A & B SOURCE switch selects either Channel 1,
Channel 2, a composite of both, or, for A-Trigger, the EXT
INPUT as the trigger source. The A COUPL switch offers
a means of accepting or rejecting certain components of
the trigger signals that are coupled to the A Trigger Gen-
erator and also selects line trigger.
Trigger Switching
Logic levels used to select the desired trigger mode are
generated by programmed array logic (PAL), U555,
depending on input signals from A 8 B SOURCE switch
S555, A COUPL switch S392 and the two Vertical MODE
switches 5545 and 5550 (+XY & U540). For the dis-
cussion below, the appropriate levels to implement the
function will be mentioned, but if greater detail is
desired, the inputs to U555 for thevarious switch settings
are shown in Table 3-1 and the logic equations for the
output levels are shown in Table 3-2.
lnternal Trigger
Signals from the Vertical Preamplifiers drive the lnternal
Trigger Amplifier with channel selection determined by
the Vertical and Horizontal MODE switches.
Trigger pickoff from the Preamplifiers is accomplished
by (2302 and Q303 for Channel 1 and (2327 and Q328 for
Channel 2. The circuitry associated with Channel 2 is the
same as that for Channel 1 except that it does not have a
trigger offset adjustment.
Signals from the Channel 1 Preamplifier are applied to
Q302 and (2303. These emitter-follower transistors each
drive one input transistor in U310, and the collectors of
the U31O input transistors in turn supply emitter current to
two current-steering transistors. The compensation and
biasing network connected to the emitters of the input
transistors in U310 is fixed for Channel 2 but not for
Channel 1. Potentiometer R309 adjusts the emitter bias
levels of the two input transistors so that dc offsets
between channels can be matched.
The base bias voltages of one transistor in each output
differential amplifier pair is fixed by the divider network
composed of R321 and R322. The other base voltage is
controlled by the CHI-TR(L) from line U555. When the
CHI-TR(L) signal is HI, the transistors in each output pair
with the collectors connected together are biased on
and the other transistors are off. The collector signal cur-
rents are equal in magnitude but opposite in polarity and
signal cancellation occurs. If the CHI JR(L) signal is LO,
the other transistors in each pairwill be biased on and an
output signal will be developed across R314 and R315 to
drive the lnternal Trigger Amplifier.
lnternal trigger sources are chosen by the A & B
SOURCE switch with the A COUPL switch set to a
position other than A LINE SOURCE. This causes
a
HI
output on U555, pin 14, and a LO on pins 12 and 13,
turning Q392 and Q399 ON, which reverse biases CR393
and CR399 to prevent external trigger signals or the line
trigger signal from reaching the A Trigger Generator.
Signals from the lnternal Trigger Amplifier are passed to
the A Trigger Generator through CR372, which is
forward-biased because Q369 is OFF.
Table 3-1
Front Panel Trigger Swltch Setting
t o PAL lnput Decoding
lnput Q (Pin
8
of
U555)
I s
supplied by
U565C.
Scans by
ARTEK
MEDL4
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