Vertical Preamplifiers - Tektronix 2235A Instruction Manual

Theory of Operation
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2235A Instruction
In the fast path, input signals are coupled through R6,
signal produced by the transistors connected to R38 and
C6, (213, and Q18 to the circuit output. By adjusting R47,
the overall gain of the amplifier will decrease. Potenti-
the gain in both paths is matched. Input offset voltage
ometer R25 adjusts the balance of the amplifier so there
compensation for U10 is provided by R10 to eliminate
is minimal dc trace shift as the VOLTS/DIV Variable con-
trace shifts when switching between Volts/Div settings.
trol is rotated.
The Gain Switching Network divides down the Buffer
Amplifier output signal for application to the Paraphase
Amplifier and has an output impedance of 75 ohms for all
Volts/Div switch settings. The particular VoltsIDiv switch
setting will determine which contacts of S10 are closed
and therefore whether the Paraphase Amplifier will
receive a t i , t 2 , t 4 , or t 1 0 signal.
Incorporated in the Channel 2 Paraphase Amplifier is
circuitry to invert the polarity of the Channel 2 signal.
Diodes CR85 and CR88 will route current from R91 and
R92 to the output pair
not
connected to R89 through
INVERT switch S90. When the switch is out, the transistor
pairs in U80 are biased as they are in U30 and there is no
trace inversion. For the IN position of S90, connections
to the bases of the output transistor pairs are reversed to
produce an inverted channel 2 trace. Potentiometer R75
Paraphase Amplifier
is adjusted so that there is minimal dc trace shift as the
INVERT button is changed between the IN and OUT
The Paraphase Amplifier converts the single-ended sig-
positions.
nal from the Gain Switching Network into a differential
signal for application to the Vertical Preamplifier.
Included in the circuitry is switching that provides extra
VERTICAL PREAMPLIFIERS
gain for the mV position
Of
the
switch*
The Vertical Preamplifier, shown on Diagram 2, utilizes
adjustments for amplifier dc balance, and circuitryforthe
differential signal current
from
the Paraphase Amplifierto
Variable VoltsIDiv function. Additionally, the Channel 2
produce differential output current to drive the Delay Line
Paraphase Amplifier contains circuitry to invert the Chan-
Driver.
trigger signals for the Trigger circuitry are
nel 2 display.
picked-off and channel selection for the crt display is
The signal from the Gain Switching Network is applied to
the base of one input transistor in U30. The other input
transistor is biased by the divider network composed of
R30, R31, and R33 to a level that will produce a null
between the outputs of U30 (no trace shift on the crt
screen) when the VOLTS/DIV control is switched
between 5 mV and 2 mV. The input transistors buffer the
signal voltages and drive the input differential pair. Emit-
ter current for the differential input pair is supplied by
R21, R22, R23, and R25, with R29 serving as the gain-
setting resistor between the two emitters. In the 2 mV
position, amplifier gain is increased by closing contact
15 of S10 to shunt R29 with R26.
The collector current through the differential input pair
serves as emitter current for the two differential output
transistor pairs. Base bias voltages for the two output
pairs are generated by the current through the diodes at
pins 7 and 14, and are controlled by R39 and the network
composed of R41, R42, and variable gain control R43.
Monolithic IC U30 has matched transistor charac-
teristics, so the ratio of currents in the two diodes
determines the current ratios in the output transistor
pairs. As VOLTSIDIV Variable potentiometer R43 is
rotated from the calibrated to uncalibrated position, the
conduction level of the transistors connected to R35 will
increase. Since the transistor pair outputs are cross-
wired, this increased conduction will subtract from the
. .
controlled by the Channel Switch circuitry.
Cornmon-base transistors Q102 and Q103 convert
differential current from the Paraphase Amplifier into
level-shifted voltages that drive the bases of the input
transistors of U130 and the Internal Trigger circuitry.
Emitter current for the differential input pair is supplied by
(2114 and Q115. POSITION control R112 adjusts the
base voltages through U120A and B to provide position
information. The collector current of the differential input
pair of U130 serves as emitter current for two differential
output pairs. One of the collectors of each output pair is
grounded and the other provides output drive to the
Delay Line Driver. The base voltages of the transistors
with grounded collectors are held at ground potential by
R136. The basevoltages of the other transistors are con-
trolled by the Channel Switch and Trigger View circuitry.
When Channel 1 is selected to drive the Delay Line
Driver, the Q output of U540A is HI. The transistors with
the ungrounded collectors will then be forward-biased
and the Channel 1 signal will be conducted through to
the Delay Line Driver. If Channel 1 is not selected, then
the Q output of U540A is LO. The transistors with the
ungrounded collectors are then reverse-biased and the
output signals will be conducted to ground by the other
transistor pair. The gain of the Preamplifier is set by
adjusting R145 to determine how much signal current
will be shunted between the two differential outputs.
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by ARTEK MEDLQ