Tektronix 2235A Instruction Manual page 62

Theory of Operation- 2235A Instruction
for both the B Miller Sweep and the B Z-Axis Switching
Logic circuits.
In the Runs After Delay mode CR626 is reverse-biased,
and a LO is placed on the D input of U670A. During the
previous holdoff period, U680D pin 13 strobed LO. The
output of the flip-flop composed of U680C and U680D
went HI and the output of U660F went LO. This placed a
LO on the S input of U670A and a HI on the R input,
causing the flip-flop to be reset. ' T he LO on pin 2 and HI
on pin 3 of U670A are converted to l T L levels by Q630
and Q631. The resulting HI on the collector of Q630 turns
Q709 on, preventing the B Miller Sweep from running.
Once the A Sweep voltage at U655, pin 3, exceeds the
voltage at pin 2, the comparator output will go LO. The
U680C-U680D flip-flop will change output states and
cause U670A to be set. Q709 is shut off and the B M~ller
Sweep Generator will produce a linear ramp. This also
sets the output of U665D LO to unblank the trace. If the B
Sweep ramp voltage reaches about 12 V , sweep-end
comparator Q643 will turn on and cause the output of
U665D to go HI. The B Miller Sweep Generator will con-
tinue to run, but the trace will be blanked because the
B-GATE(L) line is HI which reverse biases CR817. Once
the ramp is at approximately 13 V , VR712 will conduct
and prevent the voltage from increasing further.
The B Sweep Generator will be reset for another sweep
by one of two means. If the A Sweep doesn't end before
the B Sweep, the Generator will not be reset until the
ALT-SYNC line goes from HI to LO to change the
U680C-U680D flip-flop output states. The R input of
U670A goes HI causing the collector of Q630 to be HI,
resetting the B Swehp Generator. Depending on the set-
tings of the A AND B SECIDIV switches, the A Sweep
may end before the B Sweep. If this occurs, the
ALT SYNC line will go LO at the end of the A Sweep and
cause an immediate resetting of the Generator. In either
case, a new sweep will be initiated the next time the A
Sweep voltage at ~ 6 5 5 , pin 3, exceeds the voltage at pin
2.
When not in the Runs After Delay mode, the output of
U660Dis LO, a HI is placed on the D input of U670A, and
the circuitry connected to U660F operates as described
above. When the output of U660F goes HI, U660A no
longer holds U670A reset, allowing the Q output to be
clocked HI by the first B trigger signal from U605. The
collector of Q630 will go LO initiating a B Sweep.
Alternate Display Switching Logic
The Alternate Display Switching Logic circuitry controls
both the Horizontal Amplifier sweep switching and the B
Z-Axis Logic switching.
Horizontal MODE switch S648 selects the input logic
levels that are applied to the circuitry. In the A Horizontal
Mode, the R input of U670B is held HI through Q670, and
the S input is LO. This holds U670B reset. The LO on pin
15 and HI on pin 14 result in the A-DISP line at the col-
lector of Q684 being HI, which allows only the A Sweep
to be passed to the Horizontal Amplifier. In the B Hori-
zontal mode, U670B is held set, allowing only the B
Sweep to reach the Horizontal Amplifier.
With S648 set to ALT, and for all settings of the Vertical
MODE switches except BOTH-ALT, the VALT2(L) signal
applied to U660E is HI while the S and R inputs of U670B
are both LO. The LO output of U660E causes the output of
U680B to be HI, and whenever the ALT-SYNC signal
applied to pin 1 of U680A goes LO, the gate output will
change from LO to HI and clock U670B. The outputs of
U670B will toggle with each ALT-SYNC signal transition
to alternately enable the A and B Sweeps to reach the
Horizontal Amplifier. Whenever the B Sweep is selected
for display , the collector of Q687 is HI, and this level is
applied to U665C, pin 10. Pin 9 is also HI, so the SEP(L)
signal from U665C will be LO to enable the A/B Sweep
Separation circuitry.
When the CH 1 -BOTH-CH 2Vertical MODE switch is set
to BOTH, the ADD-ALT-CHOP switch becomes func-
tional. In the ALT Vertical MODE position the VALT2(L)
signal is LO, the HALT signal is HI, and the
CHI-SELECTED signal is a l T L square wave that
switches states at the end of the A Sweep. Input pin 4 of
U680B will be HI and the gate output will be the inverse of
the CHI SELECTED signal. This output signal is
~ ~ ~ ~ e d k i t h the ALT-SYNC signal by U680A to clock
U670B. Whenever the ALT-SYNC signal goes LO at the
end of a sweep and the CHI-SELECTED signal
switches from LO to HI, U670B will be clocked. Since
only positive transitions on the clock input will cause the
flip-flop to change output states, two A Sweeps are
required to cause the flip-flop output levels to switch.
With this switching arrangement, the crt will first display
the two A Intensified Sweeps and then the two Alternate
B Sweeps.
B 2-Axis Logic
The B Z-Axis Logic circuitry switches signal current
levels to drive the Z-Axis Amplifier for both the B and the
A Intensified Sweep displays. The current supplied is
summed with the other signal inputs on the Z-Drive line.
When the Horizontal MODE switch is in the ALT position,
pin 5 of U665B is HI. The outputs of U670B and the
B GATE(L) signal from the output of U665D together with
the INTENSITY controls determine the intensity of the A
and B Sweeps.
Scans by AR
TEK MEDL4
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