Altera Arria V GX Reference Manual
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Altera Arria V GX Reference Manual

Altera Arria V GX Reference Manual

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Arria V GX Starter Board Reference Manual
Arria V GX Starter Board
Reference Manual
101 Innovation Drive
San Jose, CA 95134
www.altera.com
MNL-01069-1.4
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  • Page 1 Arria V GX Starter Board Reference Manual Arria V GX Starter Board Reference Manual 101 Innovation Drive San Jose, CA 95134 www.altera.com MNL-01069-1.4 Feedback Subscribe...
  • Page 2 © 2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html.

  • Page 3: Table Of Contents

    Featured Device: Arria V GX FPGA ........
  • Page 4 How to Contact Altera ........

  • Page 5: Chapter 1. Overview

    The Arria V GX starter board provides a hardware platform for developing and prototyping low-power, high-performance, and logic-intensive designs using Altera’s Arria V GX FPGA device. The board provides a wide range of peripherals and memory interfaces to facilitate the development of Arria V GX designs.

  • Page 6: Board Component Blocks

    Chapter 1: Overview Board Component Blocks Board Component Blocks The starter board features the following major component blocks: ■ One Arria V GX 5AGXFB3H4F35C4N FPGA in a 1152-pin FineLine BGA (FBGA) package 362,000 LEs ■ 136,880 adaptive logic modules (ALMs) ■...
  • Page 7 Four general user switches ■ Power supply ■ 19-V (laptop) DC input ■ PCI Express edge connector power ■ ■ Mechanical PCI card standard size (6.600" x 4.199") ■ September 2015 Altera Corporation Arria V GX Starter Board Reference Manual...

  • Page 8: Development Board Block Diagram

    1–4 Chapter 1: Overview Development Board Block Diagram Development Board Block Diagram Figure 1–1 shows a block diagram of the Arria V GX starter board. Figure 1–1. Arria V GX Starter Board Block Diagram LVDS/Single-Ended 256-MB Port A DDR3 Type-B Embedded USB 2.0...

  • Page 9: Introduction

    2. Board Components Introduction This chapter introduces the major components on the Arria V GX starter board. Figure 2–1 illustrates the component locations and Table 2–1 provides a brief description of all component features of the board. A complete set of schematics, a physical layout database, and GERBER files for the development board reside in the Arria V GX starter kit documents directory.

  • Page 10: Board Overview

    2–2 Chapter 2: Board Components Board Overview Board Overview This section provides an overview of the Arria V GX starter board, including an annotated board image and component descriptions. Figure 2–1 shows an overview of the board features. Figure 2–1. Overview of the Arria V GX Starter Board Features...
  • Page 11 Chapter 2: Board Components 2–3 Board Overview Table 2–1. Arria V GX Starter Board Components (Part 2 of 3) Board Reference Type Description USB interface for programming and debugging the FPGA through On-Board USB-Blaster II embedded USB-Blaster II JTAG via a type-B USB cable.
  • Page 12 2–4 Chapter 2: Board Components Board Overview Table 2–1. Arria V GX Starter Board Components (Part 3 of 3) Board Reference Type Description General User Input/Output D20–D23 User LEDs Four user LEDs. Illuminates when driven low. User DIP switch Quad user DIP switches. When the switch is ON, a logic 0 is selected.

  • Page 13: Featured Device: Arria V Gx Fpga

    Featured Device: Arria V GX FPGA Featured Device: Arria V GX FPGA The Arria V GX starter board features a Arria V GX 5AGXFB3H4F35C4N device (U1) in a 1152-pin FBGA package. For more information about Arria V device family, refer to the Arria V Device Handbook.
  • Page 14 CH 0 Channels Per Bank Transceiver Bank Table 2–4 lists the Arria V GX device I/O and transceiver pin count and usage by function on the board. Table 2–4. Arria V GX Device I/O and Transceiver Pin Count Function I/O Standard...

  • Page 15: Max V Cpld 5M2210 System Controller

    Chapter 2: Board Components 2–7 MAX V CPLD 5M2210 System Controller MAX V CPLD 5M2210 System Controller The board utilizes the 5M2210 System Controller, an Altera MAX V CPLD, for the following purposes: ■ FPGA configuration from flash ■ Power measurement Fan control (shared with the FPGA) ■...
  • Page 16 FPGA_CONFIG_D12 2.5-V FPGA configuration data FPGA_CONFIG_D13 2.5-V FPGA configuration data FPGA_CONFIG_D14 2.5-V FPGA configuration data FPGA_CONFIG_D15 2.5-V FPGA configuration via protocol done LED FPGA_CVP_CONFDONE 2.5-V FPGA configuration clock FPGA_DCLK Arria V GX Starter Board September 2015 Altera Corporation Reference Manual...
  • Page 17 FSM data bus FSM_D1 2.5-V FSM data bus FSM_D2 2.5-V FSM data bus FSM_D3 2.5-V FSM data bus FSM_D4 2.5-V FSM data bus FSM_D5 2.5-V FSM data bus FSM_D6 September 2015 Altera Corporation Arria V GX Starter Board Reference Manual...
  • Page 18 25-MHz clock to on-board USB-Blaster II for sending 2.5-V M570_CLOCK FACTORY command Low signal to disable the on-board USB-Blaster II when 2.5-V M570_PCIE_JTAG_EN PCI Express is the master to the JTAG chain Arria V GX Starter Board September 2015 Altera Corporation Reference Manual...
  • Page 19 Reserved for future use USB_CFG1 2.5-V Reserved for future use USB_CFG2 2.5-V Reserved for future use USB_CFG3 2.5-V Reserved for future use USB_CFG4 2.5-V Reserved for future use USB_CFG5 September 2015 Altera Corporation Arria V GX Starter Board Reference Manual...

  • Page 20: Fpga Configuration

    FPGA Configuration This section describes the FPGA, flash memory, and MAX V CPLD 5M2210 System Controller device programming methods supported by the Arria V GX starter board. The Arria V GX starter board supports the following three configuration methods: ■...

  • Page 21: Flash Memory Programming

    FPGA designs including hardware, software, or both in an industry-standard S-Record File (.flash) and write the design to the user hardware page (page 1) of the flash memory over the network. September 2015 Altera Corporation Arria V GX Starter Board Reference Manual...

  • Page 22: Fpga Programming From Flash Memory

    The PFL megafunction is a block of logic that is programmed into an Altera programmable logic device (FPGA or CPLD). The PFL functions as a utility for writing to a compatible flash memory device. This...
  • Page 23 FLASH_D [31:16] FLASH_CEn1 FLASH_OEn FLASH_WEn FLASH_RYBSYn1 FLASH_CLK FLASH_RESETn FLASH_WPn FLASH_ADVn 10 kΩ For information about the flash memory map storage, refer to the Arria V GX Starter Kit User Guide. September 2015 Altera Corporation Arria V GX Starter Board Reference Manual...

  • Page 24: Fpga Programming Over External Usb-Blaster

    PC. The external USB-Blaster connects to the board through the JTAG header (J9). For more information on the following topics, refer to the respective documents: ■ Board Update Portal and PFL design, refer to the Arria V GX Starter Kit User Guide. ■ PFL megafunction, refer to Parallel Flash Loader Megafunction User Guide.

  • Page 25: Setup Elements

    Table 2–10. Switch and Push Button Component References and Manufacturing Information Board Manufacturer Manufacturer Description Manufacturer Reference Part Number Website C&K Components/ ITT SW1, SW2, SW4 Four-position DIP switch TDA04H0SB1 www.ittcannon.com Industries S1–S4 Push button Panasonic EVQPAC07K www.panasonic.com September 2015 Altera Corporation Arria V GX Starter Board Reference Manual...

  • Page 26: Board Settings Dip Switch

    SECURITY JTAG Chain Control DIP Switch The JTAG chain control DIP switch (SW2) either remove or include devices in the active JTAG chain. The Arria V GX is always in the JTAG chain. Table 2–12 lists the switch controls and its descriptions.

  • Page 27: Cpu Reset Push Button

    OFF : Disable fan CPU Reset Push Button The CPU reset push button, CPU_RESETn (S4), is an input to the Arria V GX DEV_CLRn pin and is an open-drain I/O from the MAX V CPLD System Controller. This push button is the default reset for both the FPGA and CPLD logic. The MAX V CPLD 5M2210 System Controller also drives this push button during power-on-reset (POR).

  • Page 28: Clock Circuitry

    The starter board includes programmable oscillators with a frequency of 100-MHz, 125-MHz, 156.25-MHz, and 409.60-MHz. Figure 2–7 shows the default frequencies of all external clocks going to the Arria V GX starter board. Figure 2–7. Arria V GX Starter Board Clocks...
  • Page 29 HSMC port A REFCLK1_QR0_N LVDS — Si5338A_CLK3_100_P 100.000 MHz LVDS fanout buffer (fanout buffer) — Si5338A_CLK3_100_N CLKINTOP_100_P LVDS Top edge—DDR3 CLKINTOP_100_N 100.000 MHz AH18 CLKINBOT_100_P LVDS Bottom edge AG18 CLKINBOT_100_N September 2015 Altera Corporation Arria V GX Starter Board Reference Manual...

  • Page 30: Off-Board Clock Input/Output

    Manufacturer Manufacturer Website Reference Part Number Programmable LVDS quad-clock 125M, 409.6M, Silicon Labs Si5338A-A01343-GM www.silabs.com 156.25M, 100M defaults 148.50 MHz LVDS voltage Silicon Labs 571FDB000159DG www.silabs.com controlled crystal oscillator Arria V GX Starter Board September 2015 Altera Corporation Reference Manual...

  • Page 31: General User Input/Output

    Board references S5, S6, and S7 are push buttons that allow you to interact with the Arria V GX. When you press and hold down the switch, the device pin is set to logic 0; when you release the switch, the device pin is set to logic 1. There are no board-specific functions for these general user push buttons.

  • Page 32: User-Defined Dip Switch

    Board references D20 through D23 are four user-defined LEDs. The status and debugging signals are driven to the LEDs from the designs loaded into the Arria V GX. There are no board-specific functions for these LEDs. Table 2–22 lists the general LED schematic signal names and their corresponding Arria V GX pin numbers.

  • Page 33: Hsmc Leds

    LEDs to display the functions as listed in Table 2–26. The LEDs are driven by the Arria V GX. Table 2–26 lists the PCI Express LED schematic signal names and their corresponding Arria V GX GX pin numbers.

  • Page 34: Character Lcd

    You can also use the header for debugging or other purposes. Table 2–28 summarizes the character LCD pin assignments. The signal names and directions are relative to the Arria V GX. Table 2–28. Character LCD Pin Assignments, Schematic Signal Names, and Functions Board Arria V GX...

  • Page 35: Components And Interfaces

    2×16 character display, 5×8 dot matrix Lumex Inc. LCM-S01602DSR/C www.lumex.com Components and Interfaces This section describes the starter board's communication ports and interface cards relative to the Arria V GX. The development board supports the following communication ports: ■ PCI Express ■ 10/100/1000 Ethernet HSMC ■...

  • Page 36: Pci Express

    Components and Interfaces PCI Express The Arria V GX starter board is designed to fit entirely into a PC motherboard with a ×8 PCI Express slot that can accommodate a full height long form factor add-in card. This interface uses the Arria V GX's PCI Express hard IP block, saving logic resources for the user logic application.
  • Page 37 2–29 Components and Interfaces Table 2–31 summarizes the PCI Express pin assignments. The signal names and directions are relative to the Arria V GX. Table 2–31. PCI Express Pin Assignments, Schematic Signal Names, and Functions Board Arria V GX Schematic Signal Name...

  • Page 38: 10/100/1000 Ethernet

    The starter board supports 10/100/1000 base-T Ethernet using an external Marvell 88E1111 PHY and Altera Triple-Speed Ethernet MegaCore MAC function. The PHY-to-MAC interface employs a RGMII interface to the Arria V GX. The MAC function must be provided in the FPGA for typical networking applications.

  • Page 39: Hsmc

    SPI4.2 interface (17 LVDS channels), three input and output clocks, as well as JTAG and SMB signals. The LVDS channels can be used for CMOS signaling or LVDS. The HSMC is an Altera-developed open specification, which allows you to expand the functionality of the development board through the addition of daughtercards (HSMCs).
  • Page 40 HSMA_TX_N7 1.5-V PCML Transceiver RX bit 7n HSMA_RX_N7 1.5-V PCML Transceiver TX bit 6 HSMA_TX_P6 1.5-V PCML Transceiver RX bit 6 HSMA_RX_P6 1.5-V PCML Transceiver TX bit 6n HSMA_TX_N6 Arria V GX Starter Board September 2015 Altera Corporation Reference Manual...
  • Page 41 Dedicated CMOS I/O bit 3 HSMA_D3 AM10 LVDS or 2.5-V LVDS TX bit 0 or CMOS bit 4 HSMA_TX_D_P0 AP11 LVDS or 2.5-V LVDS RX bit 0 or CMOS bit 5 HSMA_RX_D_P0 September 2015 Altera Corporation Arria V GX Starter Board Reference Manual...
  • Page 42 LVDS or 2.5-V LVDS TX bit 8n or CMOS bit 42 HSMA_TX_D_N8 LVDS or 2.5-V LVDS RX bit 8n or CMOS bit 43 HSMA_RX_D_N8 LVDS or 2.5-V LVDS TX bit 9 or CMOS bit 44 HSMA_TX_D_P9 Arria V GX Starter Board September 2015 Altera Corporation Reference Manual...
  • Page 43 LVDS or 2.5-V LVDS or CMOS clock out 2 or CMOS bit 78 HSMA_CLK_OUT_N2 LVDS or 2.5-V LVDS or CMOS clock in 2 or CMOS bit 79 HSMA_CLK_IN_N2 2.5-V CMOS HSMC port A presence detect HSMA_PRSNTn September 2015 Altera Corporation Arria V GX Starter Board Reference Manual...

  • Page 44: Sdi Video Output/Input

    The cable equalizer supports operation at 270 Mbit SD, 1.5 Gbit HD, and 2.97 Gbit dual-link HD modes. Control signals are allowed for bypassing or disabling the device, as well as a carrier detect or auto-mute signal interface. Arria V GX Starter Board September 2015 Altera Corporation Reference Manual...
  • Page 45 Signal Name Pin Number AD24 2.5-V Equalizer bypass enable SDI_RX_BYPASS AD23 2.5-V Device enable SDI_RX_EN 1.5-V PCML SDI video input P SDI_RX_P 1.5-V PCML SDI video input N SDI_RX_N September 2015 Altera Corporation Arria V GX Starter Board Reference Manual...

  • Page 46: Hdmi Video Output

    Table 2–42. HDMI Video Output Component Reference and Manufacturing Information Board Manufacturing Manufacturer Description Manufacturer Reference Part Number Website 19-pin HDMI connector Samtec HDMI-19-01-F-SM www.samtec.com TMDS level shifter ST Microelectronics STHDLS101T www.st.com Arria V GX Starter Board September 2015 Altera Corporation Reference Manual...

  • Page 47: Memory

    DDR3 pin assignments, signal names, and functions. The signal names and types are relative to the Arria V GX in terms of I/O setting and direction. Table 2–43. DDR3 Device Pin Assignments, Schematic Signal Names, and Functions (Part 1 of 4)
  • Page 48 Data bus byte lane 1 DDR3_DQ15 Differential 1.5-V SSTL Data strobe P byte lane 0 DDR3_DQS_P0 Class I Differential 1.5-V SSTL Data strobe N byte lane 0 DDR3_DQS_N0 Class I Arria V GX Starter Board September 2015 Altera Corporation Reference Manual...
  • Page 49 1.5-V SSTL Class I Data bus byte lane 2 DDR3_DQ18 1.5-V SSTL Class I Data bus byte lane 2 DDR3_DQ19 1.5-V SSTL Class I Data bus byte lane 2 DDR3_DQ20 September 2015 Altera Corporation Arria V GX Starter Board Reference Manual...

  • Page 50: Synchronous Sram

    The theoretical bandwidth of this 32-bit interface is 6.4 Gbps for continuous bursts. The read latency for any address is two clocks while the write latency is one clock. Arria V GX Starter Board September 2015 Altera Corporation Reference Manual...
  • Page 51 2.5-V Data bus FSM_D7 AG26 2.5-V Data bus FSM_D8 AH29 2.5-V Data bus FSM_D9 AG27 2.5-V Data bus FSM_D10 AH27 2.5-V Data bus FSM_D11 AH26 2.5-V Data bus FSM_D12 September 2015 Altera Corporation Arria V GX Starter Board Reference Manual...
  • Page 52 Data bus parity byte lane 3 SRAM_DQP3 AF22 2.5-V Global write enable SRAM_GWN AG21 2.5-V Burst sequence selection SRAM_MODE AL17 2.5-V Output enable SRAM_OEN AD21 2.5-V Power sleep mode SRAM_ZZ Arria V GX Starter Board September 2015 Altera Corporation Reference Manual...

  • Page 53: Flash

    The signal names and types are relative to the Arria V GX in terms of I/O setting and direction. Table 2–47. Flash Pin Assignments, Schematic Signal Names, and Functions (Part 1 of 4)
  • Page 54 Flash B (U13) AJ20 2.5-V Address valid FLASH_ADVN AK20 2.5-V Chip enable FLASH_CEN1 AJ22 2.5-V Clock FLASH_CLK AL22 2.5-V Output enable FLASH_OEN AG20 2.5-V Ready FLASH_RDYBSYN1 AH22 2.5-V Reset FLASH_RESETN Arria V GX Starter Board September 2015 Altera Corporation Reference Manual...
  • Page 55 2.5-V Data bus FSM_D21 AM28 2.5-V Data bus FSM_D22 AL26 2.5-V Data bus FSM_D23 AL25 2.5-V Data bus FSM_D24 AM26 2.5-V Data bus FSM_D25 AM25 2.5-V Data bus FSM_D26 September 2015 Altera Corporation Arria V GX Starter Board Reference Manual...

  • Page 56: Power Supply

    Laptop-style DC input 19.0 25-W PCI Express edge connector 12.0 75-W PCI Express edge connector 12.0 An on-board multi-channel analog-to-digital converter (ADC) measures the current for several specific board rails. Arria V GX Starter Board September 2015 Altera Corporation Reference Manual...

  • Page 57: Power Distribution System

    MAX V VCCint (500 mA) MAX II VCCint +/- 5% Board Main Power Rails 1.0 V LTC3025-1 250 mA 1.0 V LDO Ethernet PHY Arria V Power (500 mA) +/- 5% September 2015 Altera Corporation Arria V GX Starter Board Reference Manual...

  • Page 58: Power Measurement

    Description A5_VCCINT FPGA core and periphery power VCCL_GXB XCVR analog clock network A5_VCCL_VCCR_VCCT_GXB VCCR_GXB XCVR analog receive VCCT_GXB XCVR analog transmit VCCIO_8A, A5_VCCIO_1.5V VCCIO_8B, VCCIO bank 8 (DDR3) VCCIO_8C Arria V GX Starter Board September 2015 Altera Corporation Reference Manual...
  • Page 59 Table 2–51. Power Measurement ADC Component Reference and Manufacturing Information Manufacturing Manufacturer Board Reference Description Manufacturer Part Number Website 8-channel differential 24-bit ADC Linear Technology LTC2418CGN#PBF www.linear.com September 2015 Altera Corporation Arria V GX Starter Board Reference Manual...

  • Page 60: Statement Of China-Rohs Compliance

    Ethers (Pb) (Cd) (Hg) biphenyls (PBB) (Cr6+) (PBDE) Arria V GX starter board 12 V power supply Type A-B USB cable User guide Notes to Table 2–52: (1) 0 indicates that the concentration of the hazardous substance in all homogeneous materials in the parts is below the relevant threshold of the SJ/T11363-2006 standard.

  • Page 61: Additional Information

    Additional Information This chapter provides additional information about the document and Altera. Board Revision History The following table lists the versions of all releases of the Arria V GX starter board. Version Release Date Description Production silicon October 2012 Production device.

  • Page 62: Typographic Conventions

    Email Subscription Management Center page of the Altera website, where you can sign up to receive update notifications for Altera documents. The feedback icon allows you to submit feedback to Altera about the document. Methods for collecting feedback vary as appropriate for each document.

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