Fifo Write Transaction; Dlplcrc910Evm Dip Switch (Sw2); Figure 3-4. Fifo Write Transaction Timing Diagram; Table 3-11. Dlplcrc910Evm Dip Switch (Sw2) - Texas Instruments DLPLCRC910EVM User Manual

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3.7.2 FIFO Write Transaction

The USB GPIF FIFO is used to transfer image data from the USB GPIF to the user image buffer in the Apps
FPGA. The FIFO size is 256 words of 16 bits each. FIFO write transactions are always 256 words (512 bytes) in
length.
FIFO write transaction timing is shown in
Idle
(48 MHz)
usb_if_clock
usb_fd(15:8)
usb_fd(7:0)
usb_ctrl(2:0)
111b

3.8 DLPLCRC910EVM Dip Switch (SW2)

The DLPLCRC910EVM houses a dip switch (SW2) whose switch settings are used by the Apps FPGA as
described in Table 3-11.
The inputs connected to DLPLCRC910EVM SW2 are pulled high through a pullup resistor when in the
"OFF" position [logic 1] and pulled low when in the "ON" position [logic 0]. Positions 0 and 1 are not
enabled when the switch is "OFF" [logic 1] and positions 2, 3, and 7 are not enabled when "ON" [logic
0].
Signal
evm_in_dip_sw(7)
evm_in_dip_sw(6)
evm_in_dip_sw(5)
evm_in_dip_sw(4)
evm_in_dip_sw(3)
evm_in_dip_sw(2)
evm_in_dip_sw(1)
evm_in_dip_sw(0)
(1) Default Positions are as seen on the physical switch.
(2) Instructs the Apps FPGA to perform the function as described in DLPC910 data sheet. These functions are replicated in register
0x0010 (section Data Loading Control
(3) Instructs the Apps FPGA to issue pwr_floatz to DLPC910. This function is replicated in register 0x0044 (section
[PWR_FLOAT] (0x0044)).
DLPU125 – JUNE 2023
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FIFO Write Transaction Timing
One Clock
Cycle
Data
Byte 1
Data
Byte 0
FIFO Write FIFO Write
111b
110b
Word Write Word Write
0

Figure 3-4. FIFO Write Transaction Timing Diagram

Table 3-11. DLPLCRC910EVM Dip Switch (SW2)

Switch Label
8
7
6
5
4
3
2
1
(0x0010)).
Copyright © 2023 Texas Instruments Incorporated
Diagram.
One Clock 253 Clock
Cycle Cycles
Data Data
Byte 3 Byte 2n+1
Data Data
Byte 2 Byte 2n
FIFO Write
110b 110b
Word Write
n
1
Note
Function
(2)
wdt_enblz
not used
not used
not used
(2)
ns_flip
(2)
comp_data
(2)
load4_enz
(3)
pwr_float
One Clock
Idle
Cycle
Data
Byte 511
Data
Byte 510
FIFO Write
111b
110b
Word Write
255
(1)
Default Position
ON [logic 0]
ON [logic 0]
ON [logic 0]
ON [logic 0]
ON [logic 0]
ON [logic 0]
OFF [logic 1]
OFF [logic 1]
Park
®
DLP DLPC910 Apps FPGA Guide
Interfaces
111b
11