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User's Guide
Powering DRA821 with TPS6594-Q1 and LP8764-Q1
This user's guide can be used as a guide for integrating the TPS6594-Q1 and LP8764-Q1 power management
integrated circuits (PMICs) into a system powering the DRA821 processor.
1
Introduction.............................................................................................................................................................................2
2 Device Versions......................................................................................................................................................................
Connections..........................................................................................................................................................3
Settings..............................................................................................................................................................10
5.2 Device Identification Settings...........................................................................................................................................
Settings..................................................................................................................................................................11
Settings....................................................................................................................................................................13
5.5 VCCA Settings.................................................................................................................................................................
5.6 GPIO Settings..................................................................................................................................................................
5.7 Finite State Machine (FSM) Settings...............................................................................................................................
Settings..............................................................................................................................................................18
Settings...................................................................................................................................................21
5.10 Miscellaneous Settings..................................................................................................................................................
Settings............................................................................................................................................................23
5.12 Multi-Device Settings.....................................................................................................................................................
5.13 Watchdog Settings.........................................................................................................................................................
6 Pre-Configurable Finite State Machine (PFSM) Settings..................................................................................................
6.1 Configured States............................................................................................................................................................
6.2 PFSM Triggers.................................................................................................................................................................
6.3 Power Sequences............................................................................................................................................................
7 Application Examples..........................................................................................................................................................
7.1 Moving Between States: ACTIVE, MCU, and RETENTION............................................................................................
Standby...........................................................................................................................................48
7.3 Entering and Existing LP_STANDBY...............................................................................................................................
7.4 GPIO8 and Watchdog......................................................................................................................................................
Resources...........................................................................................................................................................50
9 Revision History...................................................................................................................................................................
Trademarks
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is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
SLVUBY7A - OCTOBER 2020 - REVISED OCTOBER 2022
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ABSTRACT
Table of Contents
Systems................................................................................................................................9
Requirements...........................................................................................................................9
Requirements................................................................................................................10
Settings........................................................................................................................10
Copyright © 2022 Texas Instruments Incorporated
Powering DRA821 with TPS6594-Q1 and LP8764-Q1
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Summary of Contents for Texas Instruments DRA821
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Page 1: Table Of Contents
Powering DRA821 with TPS6594-Q1 and LP8764-Q1 ABSTRACT This user’s guide can be used as a guide for integrating the TPS6594-Q1 and LP8764-Q1 power management integrated circuits (PMICs) into a system powering the DRA821 processor. Table of Contents Introduction.....................................2 2 Device Versions.................................. -
Page 2: Introduction
This user’s guide defines the power distribution network (PDN) between the TPS6594-Q1 and LP8764-Q1 devices and the DRA821 processor. This document describes the platform power resource connections, digital control connections, and PMIC sequencing settings to support the different processor state transitions. The PMIC default non-volatile memory (NVM) settings, internal state transitions, and power sequences are also defined in this document. -
Page 3: Processor Connections
1.8 V), TLV7103318-Q1 dual-voltage LDO can be used to enable compliant, dual voltage, high-speed SD card operations. SLVUBY7A – OCTOBER 2020 – REVISED OCTOBER 2022 Powering DRA821 with TPS6594-Q1 and LP8764-Q1 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated... - Page 4 MCU-only mode, GPIO Retention, and DDR Retention. Please use Table 3-1 as a guide to Powering DRA821 with TPS6594-Q1 and LP8764-Q1 SLVUBY7A – OCTOBER 2020 – REVISED OCTOBER 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
- Page 5 GPIO pins remain operational. SLVUBY7A – OCTOBER 2020 – REVISED OCTOBER 2022 Powering DRA821 with TPS6594-Q1 and LP8764-Q1 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
- Page 6 GPIO_8 of TPS6594-Q1 high. Lastly, GPIO_1 of LP8764-Q1 is included in the power up sequence to enable external regulators, for options such as DDR I/O. Powering DRA821 with TPS6594-Q1 and LP8764-Q1 SLVUBY7A – OCTOBER 2020 – REVISED OCTOBER 2022 Submit Document Feedback Copyright ©...
- Page 7 DDR retention mode, and functional safety systems capable of supporting up to ASIL-D. Please use Table SLVUBY7A – OCTOBER 2020 – REVISED OCTOBER 2022 Powering DRA821 with TPS6594-Q1 and LP8764-Q1 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
- Page 8 This GPIO is not required for power sequencing or PMIC functionality and can be configured by software for a different purpose if desired. Powering DRA821 with TPS6594-Q1 and LP8764-Q1 SLVUBY7A – OCTOBER 2020 – REVISED OCTOBER 2022 Submit Document Feedback...
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Page 9: Supporting Functional Safety Systems
Supporting Functional Safety Systems 4 Supporting Functional Safety Systems By using the TPS6594-Q1 and LP8764-Q1 solution to power the DRA821 processor, the system can leverage the following PMIC functional safety features: • Independent Power Control of MCU and Main Rails •... -
Page 10: Achieving Up To Asil-D System Requirements
In the LP876441B1-Q1 and TPS6594141B-Q1 data sheet, there are multiple application-based configurations for each BUCK to operate within. Table 5-1 includes the different configurations available: Powering DRA821 with TPS6594-Q1 and LP8764-Q1 SLVUBY7A – OCTOBER 2020 – REVISED OCTOBER 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated... -
Page 11: Device Identification Settings
These settings detail the default voltages, configurations, and monitoring of the BUCK rails. All these settings can be changed though I C after startup. SLVUBY7A – OCTOBER 2020 – REVISED OCTOBER 2022 Powering DRA821 with TPS6594-Q1 and LP8764-Q1 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated... - Page 12 Enabled; Pull-down resistor BUCK4_RV_SEL Enabled Enabled BUCK4_CONF BUCK4_SLEW_RATE 5.0 mV/μs 5.0 mV/μs BUCK4_ILIM 5.5 A 7.5 A Powering DRA821 with TPS6594-Q1 and LP8764-Q1 SLVUBY7A – OCTOBER 2020 – REVISED OCTOBER 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
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Page 13: Ldo Settings
These settings detail the default voltages, configurations, and monitoring of the LDO rails. All these settings can be changed though I C after startup. Note that only TPS6594141B-Q1 device contains LDO outputs. SLVUBY7A – OCTOBER 2020 – REVISED OCTOBER 2022 Powering DRA821 with TPS6594-Q1 and LP8764-Q1 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated... -
Page 14: Vcca Settings
5.5 VCCA Settings These settings detail the default monitoring enabled on VCCA. All these settings can be changed though I after startup. Powering DRA821 with TPS6594-Q1 and LP8764-Q1 SLVUBY7A – OCTOBER 2020 – REVISED OCTOBER 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated... -
Page 15: Gpio Settings
GPIO3_PU_PD_EN Enabled; Pull-up/pull-down Enabled; Pull-up/pull-down resistor. resistor. GPIO3_DEGLITCH_EN 0x1 8 us deglitch time. 8 us deglitch time. SLVUBY7A – OCTOBER 2020 – REVISED OCTOBER 2022 Powering DRA821 with TPS6594-Q1 and LP8764-Q1 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated... - Page 16 GPIO9_PU_PD_EN Disabled; Pull-up/pull-down Disabled; Pull-up/pull-down resistor. resistor. GPIO9_DEGLITCH_EN 0x0 No deglitch, only No deglitch, only synchronization. synchronization. Powering DRA821 with TPS6594-Q1 and LP8764-Q1 SLVUBY7A – OCTOBER 2020 – REVISED OCTOBER 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
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Page 17: Finite State Machine (Fsm) Settings
SOC rail group BUCK3_GRP_SEL MCU rail group SOC rail group BUCK4_GRP_SEL MCU rail group SOC rail group SLVUBY7A – OCTOBER 2020 – REVISED OCTOBER 2022 Powering DRA821 with TPS6594-Q1 and LP8764-Q1 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated... -
Page 18: Interrupt Settings
Masked Masked GPIO8_FSM_MASK_P Low; Masking sets signal Low; Masking sets signal value to '0' value to '0' Powering DRA821 with TPS6594-Q1 and LP8764-Q1 SLVUBY7A – OCTOBER 2020 – REVISED OCTOBER 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated... - Page 19 Interrupt not generated. VCCA_OV_MASK Interrupt not generated. Interrupt not generated. VCCA_UV_MASK Interrupt not generated. Interrupt not generated. SLVUBY7A – OCTOBER 2020 – REVISED OCTOBER 2022 Powering DRA821 with TPS6594-Q1 and LP8764-Q1 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
- Page 20 Interrupt generated MCU_PWR_ERR_MAS Interrupt generated Interrupt generated SOC_PWR_ERR_MAS Interrupt generated Interrupt generated ORD_SHUTDOWN_MA Interrupt generated Interrupt generated Powering DRA821 with TPS6594-Q1 and LP8764-Q1 SLVUBY7A – OCTOBER 2020 – REVISED OCTOBER 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
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Page 21: Powergood Settings
Masked Masked PGOOD_SEL_BUCK4 Masked Masked PGOOD_SEL_2 PGOOD_SEL_BUCK5 Masked PGOOD_SEL_3 PGOOD_SEL_LDO1 Masked PGOOD_SEL_LDO2 Masked PGOOD_SEL_LDO3 Masked PGOOD_SEL_LDO4 Masked SLVUBY7A – OCTOBER 2020 – REVISED OCTOBER 2022 Powering DRA821 with TPS6594-Q1 and LP8764-Q1 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated... -
Page 22: Miscellaneous Settings
SS_EN Spread spectrum disabled Spread spectrum disabled SS_MODE Mixed dwell Mixed dwell SS_DEPTH No modulation No modulation Powering DRA821 with TPS6594-Q1 and LP8764-Q1 SLVUBY7A – OCTOBER 2020 – REVISED OCTOBER 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated... -
Page 23: Interface Settings
These settings detail whether the device is a operating as a primary or secondary in the system. These settings cannot be changed after device startup. SLVUBY7A – OCTOBER 2020 – REVISED OCTOBER 2022 Powering DRA821 with TPS6594-Q1 and LP8764-Q1 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated... -
Page 24: Watchdog Settings
• Active • MCU Only • PWR SoC Error • Retention (both DDR and GPIO retention modes) Powering DRA821 with TPS6594-Q1 and LP8764-Q1 SLVUBY7A – OCTOBER 2020 – REVISED OCTOBER 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated... - Page 25 6-1, the configured power states are described, along with the transition conditions required to move between configured states. Additionally, the transitions to hardware states, such as SAFE RECOVERY are described. SLVUBY7A – OCTOBER 2020 – REVISED OCTOBER 2022 Powering DRA821 with TPS6594-Q1 and LP8764-Q1 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
- Page 26 NSLEEP1 Figure 6-1. Pre-Configurable State Machine (PFSM) States and Transitions The definition for each power state is described below: Powering DRA821 with TPS6594-Q1 and LP8764-Q1 SLVUBY7A – OCTOBER 2020 – REVISED OCTOBER 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
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Page 27: Pfsm Triggers
TO_STANDBY RETENTION WDOG Error False True ACTIVE ACTIVE ACTIVE_TO_WARM ESM MCU Error 6 False True ACTIVE ACTIVE SLVUBY7A – OCTOBER 2020 – REVISED OCTOBER 2022 Powering DRA821 with TPS6594-Q1 and LP8764-Q1 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated... - Page 28 After completion of an OTA update, the processor is required to initiate a reset of the PMICs to apply the new NVM settings. These triggers can originate from either the TPS6594141B or the LP9876441B1. Powering DRA821 with TPS6594-Q1 and LP8764-Q1 SLVUBY7A – OCTOBER 2020 – REVISED OCTOBER 2022 Submit Document Feedback Copyright ©...
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Page 29: Power Sequences
PMICs in case of over voltage on VCCA or thermal shutdown. The timing is illustrated in Figure 6-2. SLVUBY7A – OCTOBER 2020 – REVISED OCTOBER 2022 Powering DRA821 with TPS6594-Q1 and LP8764-Q1 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated... - Page 30 If an OFF request occurs, such as the ENABLE pin of the primary TPS6594-Q1 device being pulled low, the same power down sequence occurs, except that the PMICs go to STANDBY (LP_STANDBY_SEL=0) or Powering DRA821 with TPS6594-Q1 and LP8764-Q1 SLVUBY7A – OCTOBER 2020 – REVISED OCTOBER 2022 Submit Document Feedback Copyright ©...
- Page 31 EN_MCU3V3IO_LDSW GPIO7 LP876441B1-Q1 2000 us EN_GPIORET_LDSW GPIO10 LP876441B1-Q1 2000 us EN_3V3IO_LDSW Figure 6-3. TO_SAFE_ORDERLY and TO_STANDBY Sequence SLVUBY7A – OCTOBER 2020 – REVISED OCTOBER 2022 Powering DRA821 with TPS6594-Q1 and LP8764-Q1 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
- Page 32 After the ACTIVE_TO_WARM sequence the MCU is responsible for managing the EN_DRV and recovery counter. At the end of the sequence the 'FORCE_EN_DRV_LOW' bit is cleared so that the MCU can set the ENABLE_DRV bit. Powering DRA821 with TPS6594-Q1 and LP8764-Q1 SLVUBY7A – OCTOBER 2020 – REVISED OCTOBER 2022 Submit Document Feedback...
- Page 33 Since this sequence originates from the ACTIVE state all of the regulators are on. SLVUBY7A – OCTOBER 2020 – REVISED OCTOBER 2022 Powering DRA821 with TPS6594-Q1 and LP8764-Q1 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
- Page 34 //LP876441B1 // Set CLKMON_EN, clear LPM_EN REG_WRITE_MASK_IMM ADDR=0x81 DATA=0x18 MASK=0xE3 // Clear SPMI_LPM_EN REG_WRITE_MASK_IMM ADDR=0x82 DATA=0x00 MASK=0xEF Powering DRA821 with TPS6594-Q1 and LP8764-Q1 SLVUBY7A – OCTOBER 2020 – REVISED OCTOBER 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
- Page 35 EN_GPIORET_LDSW GPIO10 LP876441B1-Q1 2000 us EN_3V3IO_LDSW Figure 6-6. PWR_SOC_ERROR with I2C_6 and I2C_7 High in both PMICs SLVUBY7A – OCTOBER 2020 – REVISED OCTOBER 2022 Powering DRA821 with TPS6594-Q1 and LP8764-Q1 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
- Page 36 REG_WRITE_MASK_IMM ADDR=0x82 DATA=0x08 MASK=0xF7 // Clear nRSTOUT REG_WRITE_MASK_IMM ADDR=0x81 DATA=0x00 MASK=0xFE // Increment Recovery Counter REG_WRITE_MASK_IMM ADDR=0xa5 DATA=0x01 MASK=0xFE Powering DRA821 with TPS6594-Q1 and LP8764-Q1 SLVUBY7A – OCTOBER 2020 – REVISED OCTOBER 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
- Page 37 This delay is always 500us plus the time set by the PFSM_DELAY1 register. This value can be changed before entering the retention state to control when the nRSTOUT pin is released. SLVUBY7A – OCTOBER 2020 – REVISED OCTOBER 2022 Powering DRA821 with TPS6594-Q1 and LP8764-Q1 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
- Page 38 14000 us H_MCU_PORz_1V8 Figure 6-9. TO_MCU Sequence with I2C_6 = 1 and I2C7 = 0 in both PMICs Powering DRA821 with TPS6594-Q1 and LP8764-Q1 SLVUBY7A – OCTOBER 2020 – REVISED OCTOBER 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
- Page 39 14000 us H_MCU_PORz_1V8 Figure 6-10. TO_MCU Sequence with I2C_6 = 0 and I2C_7 = 1 in both PMICs SLVUBY7A – OCTOBER 2020 – REVISED OCTOBER 2022 Powering DRA821 with TPS6594-Q1 and LP8764-Q1 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
- Page 40 14000 us H_MCU_PORz_1V8 Figure 6-11. TO_MCU Sequence with I2C6 = 1 and I2C_7 = 1 in both PMICs Powering DRA821 with TPS6594-Q1 and LP8764-Q1 SLVUBY7A – OCTOBER 2020 – REVISED OCTOBER 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
- Page 41 PFSM_DELAY_REG_1 register. This delay can be changed at runtime to control how quickly the signals are released after waking up from Retention or MCU_ONLY. SLVUBY7A – OCTOBER 2020 – REVISED OCTOBER 2022 Powering DRA821 with TPS6594-Q1 and LP8764-Q1 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
- Page 42 6-16. If neither I2C_6 or I2C_7 are set high, the GPIOs and DDR will not remain active, as shown in Figure 6-17. Powering DRA821 with TPS6594-Q1 and LP8764-Q1 SLVUBY7A – OCTOBER 2020 – REVISED OCTOBER 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
- Page 43 GPIO10 LP876441B1-Q1 2000 us EN_3V3IO_LDSW Figure 6-14. TO_RETENTION Sequence, I2C_6 = 1 and I2C_7=0 in both PMICs SLVUBY7A – OCTOBER 2020 – REVISED OCTOBER 2022 Powering DRA821 with TPS6594-Q1 and LP8764-Q1 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
- Page 44 GPIO10 LP876441B1-Q1 2000 us EN_3V3IO_LDSW Figure 6-15. TO_RETENTION Sequence, I2C_6=0 and I2C_7 = 1 in both PMICs Powering DRA821 with TPS6594-Q1 and LP8764-Q1 SLVUBY7A – OCTOBER 2020 – REVISED OCTOBER 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
- Page 45 2000 us EN_3V3IO_LDSW Figure 6-16. TO_RETENTION Sequence, I2C_6 = 1 and I2C_7 = 1 in both PMICs SLVUBY7A – OCTOBER 2020 – REVISED OCTOBER 2022 Powering DRA821 with TPS6594-Q1 and LP8764-Q1 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
- Page 46 2000 us EN_3V3IO_LDSW Figure 6-17. TO_RETENTION Sequence, I2C_6 = 0 and I2C_7 = 0 in both PMICs Powering DRA821 with TPS6594-Q1 and LP8764-Q1 SLVUBY7A – OCTOBER 2020 – REVISED OCTOBER 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
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Page 47: Application Examples
MCU ONLY or the ACTIVE states must be configured before entering RETENTION. Similar to the MCU SLVUBY7A – OCTOBER 2020 – REVISED OCTOBER 2022 Powering DRA821 with TPS6594-Q1 and LP8764-Q1 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated... -
Page 48: Entering And Exiting Standby
// Set the STARTUP_DEST=ACTIVE Write 0x48:0x64:0x08:0xF7 // clear interrupt of GPIO4 Write 0x48:0x4F:0x00:0xF7 // unmask interrupt for GPIO4 falling edge Powering DRA821 with TPS6594-Q1 and LP8764-Q1 SLVUBY7A – OCTOBER 2020 – REVISED OCTOBER 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated... -
Page 49: Gpio8 And Watchdog
When it is time to enable and configure the watchdog, then in addition to enabling the watchdog the WD_PWR_HOLD must be cleared. Write 0x12:0x09:0x00:0xFB // Clear WD_PWRHOLD Write 0x12:0x09:0x40:0xBF // Enable Watchdog SLVUBY7A – OCTOBER 2020 – REVISED OCTOBER 2022 Powering DRA821 with TPS6594-Q1 and LP8764-Q1 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated... -
Page 50: Additional Resources
MCU I/O load switch while GPIO3 is reserved for SOC_SAFETY_ERRORn signal......• TPS6594 GPIO9 is involved in power sequencing instead of GPIO3.............. Powering DRA821 with TPS6594-Q1 and LP8764-Q1 SLVUBY7A – OCTOBER 2020 – REVISED OCTOBER 2022 Submit Document Feedback... - Page 51 TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products. TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2022, Texas Instruments Incorporated...