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User's Guide
®
DLP
DLPC910 Apps FPGA Guide
The DLPC910 Apps FPGA Guide describes the functions and registers of the DLPC910 Applications FPGA
(Apps FPGA) designed to work with a DLP LightCrafter DLPC910 EVM (DLPLCRC910EVM) and a supported
DMD EVM. In addition, the guide provides an overview of the VHDL code and implementation.
1
Introduction.............................................................................................................................................................................4
1.1 Welcome............................................................................................................................................................................
2
Overview..................................................................................................................................................................................5
2.1
Purpose..............................................................................................................................................................................5
3
Interfaces.................................................................................................................................................................................6
3.1 LVDS high speed data interface to DLPC910....................................................................................................................
DLP9000XUV.....................................................................................................................................6
3.1.2
DLP6500......................................................................................................................................................................6
3.4 DLPC910 Initialization and Controller Reset Signals.........................................................................................................
3.5 Apps FPGA Reset Signal - apps_resetz
3.6 DLPC910 Status-Info Signals............................................................................................................................................
3.7 USB GPIF (Interface).........................................................................................................................................................
3.7.1 Apps FPGA Register Address Read-Write Transactions............................................................................................
Transaction..............................................................................................................................................11
(SW2)................................................................................................................................................12
3.10 VC-707 Push Button Switches.......................................................................................................................................
3.11 VC-707 Status LEDs......................................................................................................................................................
3.12 DLPLCRC910EVM Apps FPGA Test Points..................................................................................................................
4
Operation...............................................................................................................................................................................14
4.1 Initialization......................................................................................................................................................................
4.1.1 Initialization Prompts.................................................................................................................................................
4.1.2 Init Routine................................................................................................................................................................
LEDs.....................................................................................................................................................15
4.1.4
Errors.........................................................................................................................................................................15
4.2.1 Test Pattern Generator (TPG)...................................................................................................................................
4.2.2 DMD Data Buffer.......................................................................................................................................................
4.2.3 DMD Load State Machine.........................................................................................................................................
4.2.4 DMD Reset State Machine........................................................................................................................................
Parameters..............................................................................................................................................18
4.2.6 Synchronization Pulse...............................................................................................................................................
4.3 User DLP Control.............................................................................................................................................................
4.3.1 DLP6500 (1920 x 1080) User Image Display Example (Global)...............................................................................
4.3.4 USB GPIF FIFO Data Writes.....................................................................................................................................
4.3.5 External Trigger.........................................................................................................................................................
4.4 USB GPIF (Operation).....................................................................................................................................................
4.5 Clocks and Resets...........................................................................................................................................................
4.5.1 Reference Clocks......................................................................................................................................................
4.5.2 Clk50 and Clk100......................................................................................................................................................
DLPU125 - JUNE 2023
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ABSTRACT
Table of Contents
Target.............................................................................................................................................5
DLPC910.............................................................................................................................6
DLPC910.......................................................................................................7
.......................................................................................................................7
(SW2)..............................................................................................................................11
DMD............................................................................................................................20
Copyright © 2023 Texas Instruments Incorporated
Control.......................................................................................15
(Global).............................................................................20
Table of Contents
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DLPC910 Apps FPGA Guide
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Table of Contents
Related Manuals for Texas Instruments DLPLCRC910EVM
Summary of Contents for Texas Instruments DLPLCRC910EVM
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Page 1: Table Of Contents
The DLPC910 Apps FPGA Guide describes the functions and registers of the DLPC910 Applications FPGA (Apps FPGA) designed to work with a DLP LightCrafter DLPC910 EVM (DLPLCRC910EVM) and a supported DMD EVM. In addition, the guide provides an overview of the VHDL code and implementation. - Page 2 Code............................31 7.3.1 Source Code................................31 7.3.2 Creating the Vivado Project............................7.3.3 Compiling the Design..............................7.3.4 Simulation..................................32 8 Related Documentation from Texas Instruments......................Appendix....................................35 9.1 Abbreviations and Acronyms............................9.2 Information About Cautions and Warnings........................36 List of Figures Figure 2-1. Apps FPGA Hardware Target............................5...
- Page 3 Table 3-11. DLPLCRC910EVM Dip Switch (SW2)........................11 Table 3-12. VC-707 Dip Switch (SW2)............................12 Table 3-13. VC-707 Push Button Switches..........................12 Table 3-14. VC-707 Status LEDs...............................12 Table 3-15. DLPLCRC910EVM Apps FPGA Test Points......................13 Trademarks ™ ™ Virtex and Vivado are trademarks of AMD.
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Page 4: Introduction
Applications FPGA (Apps FPGA) as well as the organization of the VHDL code used to create. 1.1 Welcome The DLP LightCrafter DLPC910 EVM (DLPLCRC910EVM) is a great way to evaluate the highest bandwidth data rates the DLP chip portfolio offers. Designers get pixel-accurate control of all DMD micromirrors with Global, Quad, Dual and Single Block Modes available for tailoring DMD micromirror pattern timing for continuous (lamp) or solid state (switched) illuminated applications. -
Page 5: Overview
VC-707 Evaluation Board. As shown in Apps FPGA Hardware Target, the VC-707 Evaluation Board connects to the Texas Instruments (TI) DLPC910 Evaluation Module (DLPLCRC910EVM), which connects to one of three available TI DMD boards. Figure 2-1. Apps FPGA Hardware Target ®... -
Page 6: Interfaces
This section describes the apps FPGA interface signals. Apps FPGA interfaces to the DLPC910 EVM board through two high pin count FMC connectors (J500 and J501 on the DLPLCRC910EVM board). In addition to the DLPC910 interfaces, the apps FPGA uses push button switches, dip switches, and LEDs on the VC-707 evaluation board. -
Page 7: Dmd Reset And Block Clear Signals To The Dlpc910
USB GPIF. The DMD_speed_sel signal is from a set of jumpers on the DLPLCRC910EVM board. The jumper settings are used by DLPC910 controller and by Apps FPGA to determine clock frequency of the LVDS high speed interface DLP9000X and DLP9000XUV. -
Page 8: Usb Gpif (Interface)
Register addresses and data are 32 bits in width. Two 16-bit bus transactions are required to transfer 32 bits. Note Data is sampled on the falling edges of the usb_if_clk. ® DLPC910 Apps FPGA Guide DLPU125 – JUNE 2023 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated... -
Page 9: Figure 3-1. Register Address Transaction Timing Diagram
Data Write usb_ctrl(2:0) 111b 111b 111b 111b 111b 010b 010b Data Low Data High Figure 3-2. Register Data Write Transaction Timing Diagram ® DLPU125 – JUNE 2023 DLPC910 Apps FPGA Guide Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated... -
Page 10: Figure 3-3. Register Data Read Transaction Timing Diagram
0x01 0x00 0x03 0x00 usb_fd(7:0) Idle Data read– “001” Data read– “001” Idle Data read– “001” Data read – “001” Idle usb_ctrl(2:0) ® DLPC910 Apps FPGA Guide DLPU125 – JUNE 2023 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated... -
Page 11: Fifo Write Transaction
Word Write Word Write Word Write Figure 3-4. FIFO Write Transaction Timing Diagram 3.8 DLPLCRC910EVM Dip Switch (SW2) The DLPLCRC910EVM houses a dip switch (SW2) whose switch settings are used by the Apps FPGA as described in Table 3-11. Note The inputs connected to DLPLCRC910EVM SW2 are pulled high through a pullup resistor when in the "OFF"... -
Page 12: Vc-707 Dip Switch (Sw2)
Pressing SW3 halts test pattern cycling. Subsequent presses of SW3 changes to the next test pattern. SW3 controlled pattern sequencing is ended by pressing the Apps FPGA reset switch on the DLPLCRC910EVM board. 3.11 VC-707 Status LEDs The apps FPGA uses the VC-707 GPIO LEDs to indicate initialization &... -
Page 13: Dlplcrc910Evm Apps Fpga Test Points
GPIO LED 0 is illuminated by the init-run-park state machine when anomalies occur during DLPC910 initialization. 3.12 DLPLCRC910EVM Apps FPGA Test Points The DLPLCRC910EVM houses a dip switch (SW2) whose switch settings are used by the Apps FPGA as described in Table 3-15. -
Page 14: Operation
1. Completion of the Apps FPGA configuration. 2. Pressing SW1 APP RST switch on DLPLCRC910EVM (apps_resetz to the Apps FPGA). 3. ON to OFF transition by position 1 of dip switch SW2 on DLPLCRC910EVM (un-parking the system using dip switch). -
Page 15: Init Routine
Note A change to the dmd_speed_sel jumpers on the DLPLCRC910EVM requires re-running initialization (press SW1 APP RST switch). 4.1.3 GPIO Status LEDs Three VC-707 board GPIO LEDs are used to give init-run-park status: •... -
Page 16: Test Pattern Generator (Tpg)
Successive activation of SW3 selects the next test pattern in the sequence. Pressing the Apps FPGA reset switch on the DLPLCRC910EVM board re-initializes the Apps FPGA and DLP component set and return to auto pattern cycling. -
Page 17: Figure 4-3. Dmd Load State Machine
DMD reset state machine. The loader uses DLP6500 and DLP9000X look up tables, addressable by the current device row number, to determine on which rows to send phased reset requests. ® DLPU125 – JUNE 2023 DLPC910 Apps FPGA Guide Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated... -
Page 18: Dmd Reset State Machine
(User Row Command Register (0x002C)). 3. Send USB GPIF block commands to create mirror control pulses to display image data (User Block Command Register (0x0030)). ® DLPC910 Apps FPGA Guide DLPU125 – JUNE 2023 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated... -
Page 19: Dlp6500 (1920 X 1080) User Image Display Example (Global)
⁞ Burst 507 256, 16-bit words Send Data from the Apps FPGA Data Buffer to the DLPC910 - DMD Set image data modifiers if needed (ns_flip, comp_data). Use dip switch (SW2) on DLPLCRC910EVM board or use register 0x0010. Step Description... -
Page 20: Dlp9000X (2560 X 1600) User Image Display Example (Global)
⁞ Burst 1000 256, 16-bit words Send Data from the Apps FPGA Data Buffer to the DLPC910 - DMD Set image data modifiers if needed (ns_flip, comp_data). Use dip switch (SW2) on DLPLCRC910EVM board or use register 0x0010. Step Description... -
Page 21: Usb Gpif (Operation)
• usb_if_clk from the Infineon - Cypress USB interface chip A third external clock source, spare_clk, driven from the DLPLCRC910EVM, is not used by the Apps FPGA. This clock is provided as both differential and single ended signal types. 4.5.2 Clk50 and Clk100 The general-purpose clock, clk50, is used for switch debounce and by the init-run-park state machine and is a 50 MHz free-running clock. -
Page 22: Clock Domain Crossings (Cdc)
VC-707 evaluation board • vc707_in_pb_sw(7:3) from push button switches on the VC-707 evaluation board • resetz from the push button switch on DLPLCRC910EVM (SW1) ® DLPC910 Apps FPGA Guide DLPU125 – JUNE 2023 Submit Document Feedback... -
Page 23: Usb Gpif Registers
This status bit is an apps FPGA pass through of a signal from the DLPC910. ® DLPU125 – JUNE 2023 DLPC910 Apps FPGA Guide Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated... -
Page 24: Data Loading Control (0X0010)
Test pattern select chooses test pattern to display when test pattern cycling is disabled: • 0x00 – full ON pattern ® DLPC910 Apps FPGA Guide DLPU125 – JUNE 2023 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated... -
Page 25: Test Row Address (0X0018) - [Unused]
Read from DLPC910 (3:0) DMD_TYPE(3:0) Read from DLPC910 EVM_DIPSW field is the 8-bit value signaled to the Apps FPGA from the 8-position dip switch on the DLPLCRC910EVM board. Out of box logic default is 0x03. See DLPLCRC910EVM Dip Switch (SW2). -
Page 26: Usb Gpif Fifo Read Burst Size (0X0028) - [Obsolete]
Block command details are described in the DLPC910 data sheet. Forwarded block commands include the appropriate synchronization with DCLK and DVALID. ® DLPC910 Apps FPGA Guide DLPU125 – JUNE 2023 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated... -
Page 27: Loader Row Control (0X0034)
DLP chip set through the USB GPIF. ® DLPU125 – JUNE 2023 DLPC910 Apps FPGA Guide Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated... -
Page 28: Park [Pwr_Float] (0X0044)
This register is used for USB GPIF testing only. The contents of this register do not affect the Apps FPGA operation. ® DLPC910 Apps FPGA Guide DLPU125 – JUNE 2023 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated... -
Page 29: Fpga Configuration
CAUTION TI recommends that the flash memory be written with the Apps FPGA configuration memory file before connecting the VC-707 board to the DLPLCRC910EVM avoiding potential FMC connector I/O conflicts between the factory loaded VC-707 FPGA configuration and DLPC910 controller. -
Page 30: Apps Fpga Source Files And Compilation
The primary VHDL modules (.vhd) provide the main DLP control functionality of the Apps FPGA. AMD - Xilinx IP modules (.xci) are used for PLLs, FIFOs, memories, and a multiplier. ® DLPC910 Apps FPGA Guide DLPU125 – JUNE 2023 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated... -
Page 31: Modules With Multiple Instantiations
– folder for VHDL test bench files In addition, the following four files are included in the source folder: • 16x12800_coe.coe • dlp6500_load_lut.coe ® DLPU125 – JUNE 2023 DLPC910 Apps FPGA Guide Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated... -
Page 32: Creating The Vivado Project
FPGA project, the project .tcl script adds the test bench files to the project. The test bench sources are viewable in the Vivado project manager GUI, sources hierarchy window. See Figure 7-2. ® DLPC910 Apps FPGA Guide DLPU125 – JUNE 2023 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated... -
Page 33: Figure 7-2. Test Benches
Browse to select one of the test bench files of interest so that the file appears in the Simulation top module name: box. Then click on OK. Figure 7-3. Settings Dialog ® DLPU125 – JUNE 2023 DLPC910 Apps FPGA Guide Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated... -
Page 34: Figure 7-4. Vivado Waveform Window
(under the File pull-down menu, select Simulation Waveform). A waveform configuration file is supplied for each test bench to give a starting point for working with module simulations. Figure 7-4. Vivado Waveform Window ® DLPC910 Apps FPGA Guide DLPU125 – JUNE 2023 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated... -
Page 35: Related Documentation From Texas Instruments
Related Documentation from Texas Instruments 8 Related Documentation from Texas Instruments Component data sheets, technical documents, design documents, and ordering information related to the DLPC910 are found at the following links: DLPC910 Digital Controller Product Folder LightCrafter DLPC910 EVM Product Folder... -
Page 36: Information About Cautions And Warnings
® DLPC910 Apps FPGA Guide DLPU125 – JUNE 2023 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated... - Page 37 STANDARD TERMS FOR EVALUATION MODULES Delivery: TI delivers TI evaluation boards, kits, or modules, including any accompanying demonstration software, components, and/or documentation which may be provided together or separately (collectively, an “EVM” or “EVMs”) to the User (“User”) in accordance with the terms set forth herein.
- Page 38 www.ti.com Regulatory Notices: 3.1 United States 3.1.1 Notice applicable to EVMs not FCC-Approved: FCC NOTICE: This kit is designed to allow product developers to evaluate electronic components, circuitry, or software associated with the kit to determine whether to incorporate such items in a finished product and software developers to write software applications for use with the end product.
- Page 39 www.ti.com Concernant les EVMs avec antennes détachables Conformément à la réglementation d'Industrie Canada, le présent émetteur radio peut fonctionner avec une antenne d'un type et d'un gain maximal (ou inférieur) approuvé pour l'émetteur par Industrie Canada. Dans le but de réduire les risques de brouillage radioélectrique à...
- Page 40 www.ti.com EVM Use Restrictions and Warnings: 4.1 EVMS ARE NOT FOR USE IN FUNCTIONAL SAFETY AND/OR SAFETY CRITICAL EVALUATIONS, INCLUDING BUT NOT LIMITED TO EVALUATIONS OF LIFE SUPPORT APPLICATIONS. 4.2 User must read and apply the user guide and other available documentation provided by TI regarding the EVM prior to handling or using the EVM, including without limitation any warning or restriction notices.
- Page 41 Notwithstanding the foregoing, any judgment may be enforced in any United States or foreign court, and TI may seek injunctive relief in any United States or foreign court. Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2023, Texas Instruments Incorporated...
- Page 42 TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products. TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2023, Texas Instruments Incorporated...
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