Texas Instruments DS125RT410 Manual
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Texas Instruments DS125RT410 Manual

Texas Instruments DS125RT410 Manual

Low power multi-rate quad channel retimer
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DS125RT410 Low Power Multi-Rate Quad Channel Retimer
FEATURES
1
•
Each channel independently locks to data
2
rates from 9.8 to 12.5 Gbps and submultiples
•
Fast lock operation based on protocol-select
mode
•
Low latency (~300ps)
•
Adaptive equalization up to 34 dB boost at 5
GHz
•
Adjustable transmit V
•
Adjustable transmit de-emphasis to -15 dB
•
Typical Power Dissipation (EQ+CDR+DE): 150
mW / channel
•
Programmable output polarity inversion
•
Input signal detection, CDR lock
detection/indicator
•
On-chip Eye Monitor (EOM), PRBS generator
•
Single 2.5 V ±5% power supply
•
SMBus/EEPROM configuration modes
•
Operating temperature range of -40 to 85°C
•
RHS 48-pin 7 mm x 7 mm package
•
Easy pin compatible upgrade between
repeater and retimers
– DS100RT410 (EQ+CDR+DE): 10.3125 Gbps
– DS100DF410 (EQ+DFE+CDR+DE): 10.3125
Gbps
– DS110RT410 (EQ+CDR+DE): 8.5 - 11.3 Gbps
– DS110DF410 (EQ+DFE+CDR+DE): 8.5 - 11.3
Gbps
– DS125RT410 (EQ+CDR+DE): 9.8 - 12.5 Gbps
– DS125DF410 (EQ+DFE+CDR+DE): 9.8 - 12.5
Gbps
– DS100BR410 (EQ+DE): Up to 10.3125 Gbps
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
2
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Check for Samples:
: 600 to 1300 mVp-p
OD
DS125RT410
APPLICATIONS
•
Front port SFF 8431 (SFP+) optical and direct •
Input signal detection, CDR lock attach copper
•
Backplane reach extension, data retimer
•
Ethernet: 10GbE, 1GbE
•
CPRI: Line bit rate options 3–7
•
Interlaken: All lane bit rates
For other data rates and data transmission
protocols, other pin-compatible devices in the
retimer family can be used.
DESCRIPTION
The DS125RT410 is four channel retimers with
integrated signal conditioning. The devices include a
fully adaptive Continuous-Time Linear Equalizer
(CTLE), Clock and Data Recovery (CDR) and
transmit De-Emphasis (DE) driver to enable data
transmission over long, lossy and crosstalk-impaired
highspeed serial links to achieve BER < 1×10
Each channel can independently lock to data rate
from 9.8 to 12.5 Gbps, and associated sub rates (div
by 2, 4 and 8) to support a variety communication
protocols. A 25 MHz reference clock is required,
which need not be synchronous with the serial data.
The programmable settings can be applied using the
SMBus (I2C) interface, or they can be loaded via an
external EEPROM. An on-chip eye monitor and a
PRBS generator allow real-time measurement of
high-speed serial data for system bring-up or field
tuning. Flow-through pinout and single power supply
make the DS125RT410 easy to use.
The device is offered in a RHS 48-pin, 7 mm x 7 mm
package with flow-through pinout for the high speed
signals.
Copyright © 2011, Texas Instruments Incorporated
DS125RT410
SNLS459 – APRIL 2011
-15
.

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Summary of Contents for Texas Instruments DS125RT410

  • Page 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners.

  • Page 2: Typical Application Diagram

    Typical Application Diagram Line Card Switch Fabric DS125RT410 Optical Modules 10GbE SFP+ (SFF8431) CPRI ASIC QSFP ASIC Interlaken Others Back DS125RT410 Passive Copper Plane/ Plane Clean Signal Noisy Signal Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Links: DS125RT410...

  • Page 3: Connection Diagram

    RXN0 TXP1 RXP1 TXN1 RXN1 DS125RT410 7 mm x 7 mm, 0.5 mm pitch TOP VIEW RXP2 TXP2 DAP = GND RXN2 TXN2 RXP3 TXP3 RXN3 TXN3 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Links: DS125RT410...
  • Page 4 Pin is 3.3 V LVCMOS tolerant. I/O, 3.3V Clock Input / Open Drain Clock Output LVCMOS, Open External 2KΩ to 5KΩ pull-up resistor is required. Drain Pin is 3.3 V LVCMOS tolerant. Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Links: DS125RT410...

  • Page 5: Absolute Maximum Ratings

    Conditions indicate conditions at which the device is functional and the device should not be operated outside these conditions. Recommended Operating Conditions Units Supply Voltage to GND 2.375 2.625 Ambient Temperature °C Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Links: DS125RT410...

  • Page 6: Electrical Characteristics

    (3) Max momentary power supply current lasting less than 1s. The retimer may consume more power than the maximum average power rating during the time required to acquire CDR lock. (4) Allowed supply noise (mV sine wave) under typical conditions. Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Links: DS125RT410...
  • Page 7 (10) Measured with 10 MHz clock pattern output. (11) De-emphasis pulse width varies with V and de-emphasis settings. (12) Typical with no output de-emphasis, minimum output transmission channel. Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Links: DS125RT410...
  • Page 8 10 kHz to 250 MHz sinusoidal jitter frequency Jitter Transfer Measured at BER = 10 TRANS Sinusoidal jitter at 10 MHz jitter frequency CDR Lock Time Measured at 10.3125 Gbps LOCK Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Links: DS125RT410...

  • Page 9: Functional Description

    Detect Figure 1. DS125RT410 Data Path Block Diagram — One of Four Channels Device Data Path Operation The data path operation of the DS125RT410 comprises three functional sections as shown in the data path block diagram of Figure 1. The three functional sections are as follows.
  • Page 10 This process produces a recovered clock with greatly reduced jitter at jitter frequencies outside the bandwidth of the CDR Phase-Locked Loop (PLL). This is the primary benefit of using the DS125RT410 in a system. It significantly reduces the jitter present in the data stream, in effect resetting the jitter budget for the system.

  • Page 11: Device Configuration

    The DS125RT410 is designed to lock rapidly to any valid signal present at its inputs. It is also designed to detect incorrect lock conditions which can arise when the input data signals are strongly periodic. This condition is referred to as “false lock”.
  • Page 12 As an example of the usage of the registers in Table 1, assume that the retimer is required to operate in 10 GbE or 1GbE mode. By setting register 0x2f, bits 7:4, to 4'b1111, the DS125RT410 will automatically set its divider ratio and its coarse VCO tuning setting to lock to either a 10 GbE signal (at 10.3125 Gb/s) or a 1 GbE signal (at...
  • Page 13 7. Reset the retimer CDR by setting and then clearing bits 3:2 of register 0x0a. If there is a signal at the correct data rate present at the input to the DS125RT410, the retimer will lock to it. In ref_mode 3, bits 5:4 of register 0x36 are set to 2'b11, it is not necessary to set the CAP DAC values the DS125RT410 determines the correct CAP DAC values automatically.
  • Page 14 Driver Output De-Emphasis The output de-emphasis level of the DS125RT410 can be configured from a nominal setting of 0 dB to a nominal setting of -15 dB depending upon the application. Larger absolute values of the de-emphasis setting provide more pre-distortion of the output driver waveform, accentuating the high-frequency components of the output driver waveform relative to the low-frequency components.
  • Page 15 SNLS459 – APRIL 2011 The DS125RT410 can be configured to operate with a nominal rise/fall time corresponding to the maximum slew rate of the output drivers into the load capacitance. Alternatively, the DS125RT410 can be configured to operate with a slightly greater rise/fall time if desired. For the typical specifications on rise/fall time, see...
  • Page 16 SMBus slave. In applications where there is more than one DS125RT410 on the same SMBus, bus contention can result if more than one DS125RT410 tries to take command of the SMBus at the same time. The READ_EN and ALL_DONE pins prevent this bus contention.
  • Page 17 Also, in either mode, the SMBus address is latched in on the address strap lines on power-up. In SMBus slave mode, if the READ_EN pin is not tied low, the DS125RT410 will not latch in the address on its address strap lines.
  • Page 18 When the DS125RT410 is used in SMBus slave mode, the READ_EN pin must be tied low. If it is tied high or floating, the DS125RT410 will not latch in its address from the address lines on power-up. When the READ_EN pin is tied high in SMBus slave mode i.e.

  • Page 19: Register Information

    DS125RT410 is the value in register 0x00 of the control/shared register set. If you read the value in register 0x00 when bit 2 of register 0xff is set to 1, then the value returned by the DS125RT410 is the value in register 0x00 of the selected channel register set.
  • Page 20 DS125RT410 . The address strap observation bits in control/shared register 0x00 are primarily useful as a test of SMBus operation. There is no way to get the DS125RT410 to tell you what its SMBus address is unless you already know what it is.
  • Page 21 DS125RT410 to read from the EEPROM again it is necessary to set bit 5 of register 0x04, resetting the SMBus master mode. If the DS125RT410 is not in SMBus master mode, do not set this bit. After setting this bit, it should be cleared before further SMBus operations.
  • Page 22 0xff are explicitly changed by a register write to register 0xff. As noted, there is only one register with an address of 0xff, the channel select register. Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Links: DS125RT410...
  • Page 23 Driver De-emphasis Range drv_dem[2:0] Driver De-emphasis Setting<2:0> 0x18 pdiq_sel_div[2:0] VCO Divider Ratio <2:0> (Enable from Register 0x09, Bit 2) drv_sel_slow Enable Slow Rise/Fall Time on Output Driver Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Links: DS125RT410...
  • Page 24 Pattern Select <1:0> 0x31 adapt_mode[1:0] Adaptation Mode <1:0> eq_sm_fom[1:0] CTLE Adaptation Figure of Merit Type <1:0> 0x32 heo_int_thresh[3:0] HEO Interrupt Threshold <3:0> veo_int_thresh[3:0] VEO Interrupt Threshold <3:0> Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Links: DS125RT410...
  • Page 25 Merit Term b<7:0> 0x6d fom_c[7:0] Adaptation Figure of Merit Term c<7:0> 0x6e en_new_fom_ctle Enable Alternate Figure of Merit for CTLE Adaptation 0x70 eq_lb_cnt[2:0] CTLE Adaptation Look-Beyond Count <2:0> Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Links: DS125RT410...
  • Page 26 When bit 2 is subsequently cleared, the CDR state machine will resume normal operation. If a signal is present at the input to the selected channel, the DS125RT410 will attempt to lock to it and will adapt its CTLE.
  • Page 27 1. Set the DS125RT410 channel adapt mode to 0 by writing 0x0 to bits 6:5 of channel register 0x31. 2. Set the desired CTLE boost setting in register 0x3a. If the DS125RT410 loses lock and attempts to lock to a lower data rate, it will use this CTLE boost setting.
  • Page 28 CAP DAC values for this rate. The first is in register 0x08, bits 4:0, and the second is in register 0x0b, bits 4:0. The DS125RT410 will use the CAP DAC value in register 0x08 for the larger divide ratio (8) associated with the selected rate and subrate to try and acquire lock.
  • Page 29 Table 9. If there is an input signal, and if the DS125RT410 is locked to it, the VCO I-Clock, the VCO Q-Clock, and the output of the PRBS generator, if it is enabled, will be synchronous to the input signal.
  • Page 30 Now write a 1 to bit 6 of register 0x09. This enables the VCO LPF DAC which can generate a VCO control voltage internally to the DS125RT410. Once the LPF DAC is enabled, write the desired value of the LPF DAC output in register 0x1f, bits 4:0.
  • Page 31 0x26, Register 0x27, Register 0x28, Register 0x2a and Register 0x3e, bit 7 The DS125RT410 includes an internal eye opening monitor. The eye opening monitor is used by the retimer to compute a figure of merit for automatic adaptation of the CTLE. It can also be controlled and queried through the SMBus by a system controller.
  • Page 32 SMBus with no further register writes required. The external controller just reads the data from the DS125RT410 over the SMBus as fast as it can. When all the data has been read, the DS125RT410 clears the eom_start bit.
  • Page 33 The DS125RT410 can invert the polarity of the data signals by means of a register write. Writing a 1 to bit 7 of register 0x1f inverts the polarity of the output signal for the selected channel.
  • Page 34 The minimum values are set in register 0x6a. The DS125RT410 continuously monitors the horizontal and vertical eye openings while it is in lock. If the eye opening falls below the threshold set in register 0x6a, the DS125RT410 will declare a loss of lock.
  • Page 35 These spurs can cause the DS125RT410 to false lock. Using the 25 MHz reference clock, the DS125RT410 can detect when it is locked to a jitter spur. When this happens, the DS125RT410 will re-initiate the adaptation and lock sequence until it locks to the correct data rate.
  • Page 36 Register 0x2d, bits 2:0 There are eight levels of output differential voltage available in the DS125RT410, from 0.6 V to 1.3 V in 0.1 V increments. The values drv_sel_vod[2:0] in bits 2:0 of register 0x2d set the output VOD. The available VOD...
  • Page 37 Register 0x15, bits 2:0 and bit 6 Fifteen output de-emphasis settings are available in the DS125RT410, ranging from 0 dB to -15 dB. The de- emphasis values come from register 0x15, bits 2:0, which make up the bit field dvr_dem<2:0>, and register 0x15, bit 6, which is the third de-emphasis setting bit.
  • Page 38 PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Top-Side Markings Samples Drawing DS125RT410SQ/NOPB ACTIVE WQFN 1000 Green (RoHS CU SN Level-3-260C-168 HR -40 to 85 125RT410 &...

  • Page 39: Tape And Reel Information

    PACKAGE MATERIALS INFORMATION www.ti.com 24-Apr-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Reel Reel Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1 (mm) DS125RT410SQ/NOPB WQFN 1000 330.0 16.4 12.0 16.0 DS125RT410SQE/NOPB WQFN 178.0...
  • Page 40 PACKAGE MATERIALS INFORMATION www.ti.com 24-Apr-2013 *All dimensions are nominal Device Package Type Package Drawing Pins Length (mm) Width (mm) Height (mm) DS125RT410SQ/NOPB WQFN 1000 367.0 367.0 38.0 DS125RT410SQE/NOPB WQFN 213.0 191.0 55.0 Pack Materials-Page 2...

  • Page 41: Mechanical Data

    MECHANICAL DATA RHS0048A SQA48A (Rev B) www.ti.com...

  • Page 42: Important Notice

    IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue.

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