Xilinx 7 Series User Manual page 3

Date Version
08/6/2013 1.5
08/11/2014 1.6
11/17/2014 1.7
09/27/2016 1.8
UG474 (v1.8) September 27, 2016
Added Artix®-7 devices. Updated references to implementation tools.
Revised footnotes in Table 1-2
programmable in Control Signals, page
removed footnotes. Renamed or made minor revisions to
Revised sections Clock – WCLK, page
Updated Table 1-2 for new Artix 7A15T device.
Added Spartan®-7 device family (updated Preface and added
Artix®-7 7A12T and 7A25T devices to
www.xilinx.com
Revision
through Table 1-4. Revised polarity from independent to
22. Added Primitive column to
Figure 2-6
49, Clock – CLK, page
Table 1-2.
7 Series FPGAs CLB User Guide
Table 2-3 and
through Figure 2-14.
50, and Clock - C, page 51.
Table 1-1). Added