Xilinx 7 Series User Manual page 6

CLB Slice Distributed RAM Timing Model and Parameters (Available in SLICEM Only)
63
CLB Slice SRL Shift Register Timing Model and Parameters (Available in SLICEM
Only)
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Chapter 6: Advanced Topics
Using the Latch Function as Logic
Interconnect Resources
Devices Using Stacked Silicon Interconnect (SSI) Technology
6
Send Feedback
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7 Series FPGAs CLB User Guide
UG474 (v1.8) September 27, 2016