Chapter 6: Advanced Topics; Using The Latch Function As Logic - Xilinx 7 Series User Manual

Advanced Topics

Using the Latch Function as Logic

Because the latch function is level-sensitive, it can be used as the equivalent of a logic gate.
The primitives to specify this function are AND2B1L (a 2-input AND gate with one input
inverted) and OR2L (a 2-input OR gate), as shown in
X-Ref Target - Figure 6-1
As shown in
AND2B1L and OR2L primitives are instantiated, and the CK gate and CE gate enables are
held active-High. The AND2B1L combines the latch data input (the inverted input on the
gate, DI) with the asynchronous clear input (SRI). The OR2L combines the latch data input
with an asynchronous preset. Generally, the latch data input comes from the output of a
LUT within the same slice, extending the logic capability to another external input.
Because there is only one SR input per slice, using more than one AND2B1L or OR2L per
slice requires a shared common external input.
X-Ref Target - Figure 6-2
The device model shows these functions as AND2L and OR2L configurations of the
storage element.
7 Series FPGAs CLB User Guide
UG474 (v1.8) September 27, 2016
AND2B1L
Figure 6-1: AND2B1L and OR2L Components
Figure 6-2, the data and SR inputs and Q output of the latch are used when the
IN[6:1]
O6
LUT6
V
CC
SRI
Figure 6-2: Implementation of OR2L (Q = D or SRI)
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Chapter 6
Figure 6-1.
OR2L
UG474_c6_01_110210
Q
D Q
CE
CK
SR
UG474_c6_02_110310
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