Digital Input / Output; Counters - Measurement Computing PCI-2511 User Manual

PCI-2511 User's Guide

Digital input / output

Parameter
Number of I/O
Ports
Input scanning mode
Configuration
Input protection
Input high
Input low
Output high
Output low
Output current
Digital input pacing
Digital output pacing
Digital input trigger sources and modes
Digital output trigger sources
Data transfer
Sampling/update rate
Pattern generation output

Counters

Counter inputs can be scanned based on an internal programmable timer or an external clock source.
Parameter
Channels
Resolution
Input frequency
Input signal range
Input characteristics
Trigger level
Minimum pulse width
Debounce times
Time-base accuracy
Counter read pacer
Trigger sources and modes
Programmable mode
Counter mode options
Table 3. Digital input/output specifications
Specification
24
Three banks of eight.
Each port is programmable as input or output
Asynchronous, under program control at any time relative to input scanning
10 kΩ pull-up to +5 V, 20 pf to analog common
±15 kV ESD clamp diodes
+2.0 V to +5.0 V
0 to 0.8 V
>2.0 V
<0.8 V
Output 12 mA per pin, 200 mA total continuous
Onboard clock, external input scan clock (XAPCR)
Four programmable sources:
Onboard output scan clock, independent of input scan clock

Onboard input scan clock

External output scan clock (XDPCR), independent of external input scan

clock (XAPCR)
External input scan clock (XAPCR)

Refer to Table 7
Start of input scan
DMA
4 MHz max (rates up to 12 MHz are sustainable on some platforms)
Two of the 8-bit ports can be configured for 16-bit pattern generation. The
pattern can also be updated synchronously with an acquisition at up to 4 MHz.
Table 4. Counter specifications
Specification
Four independent
32 bits
20 MHz max
–5 V to 10 V
10 kΩ pull-up, ±15 kV ESD protection
TTL
25 ns high, 25 ns low
16 selections from 500 ns to 25.5 ms, positive or negative edge sensitive, glitch
detect mode or debounce mode
30 ppm (0 °C to 50 °C)
Onboard input scan clock, external input scan clock (XAPCR)
Refer to Table 7
Counter
Totalize, clear on read, rollover, stop at all Fs, 16-bit or 32-bit, any other
channel can gate the counter
31
Specifications