Counter Inputs; Mapped Channels; Counter Modes - Measurement Computing PCI-2511 User Manual

PCI-2511 User's Guide
No pre-trigger, infinite post-trigger
No pre-trigger data is acquired. Instead, data is acquired beginning with the trigger event, and is terminated
when you issue a command to halt the acquisition.
Fixed pre-trigger with infinite post-trigger
You set the amount of pre-trigger data to acquire. The system continues to acquire data until the program issues
a command to halt the acquisition.

Counter inputs

Four 32-bit counters are built into the PCI-2511. Each counter accepts frequency inputs up to 20 MHz. The
counter channels can be configured as standard counters or as multi-axis quadrature encoders.
The counters can concurrently monitor time periods, frequencies, pulses, and other event driven incremental
occurrences directly from pulse-generators, limit switches, proximity switches, and magnetic pick-ups.
Counter inputs can be read asynchronously under program control, or synchronously as part of an analog or
digital scan group.
When reading synchronously, all counters are set to zero at the start of an acquisition. When reading
asynchronously, counters may be cleared on each read, count up continually, or count until the 16 bit or 32 bit
limit has been reached. See counter mode descriptions below.

Mapped channels

A mapped channel is one of four counter input signals that can get multiplexed into a counter module. The
mapped channel can participate with the counter's input signal by gating the counter, latching the counter, and
so on. The four possible choices for the mapped channel are the four counter input signals (post-debounce).
A mapped channel can be used to:
gate the counter

decrement the counter

latch to current count to the count register

Usually, all counter outputs are latched at the beginning of each scan within the acquisition. However, you can
use a second channel—known as the mapped channel— to latch the counter output.

Counter modes

A counter can be asynchronously read with or without clear on read. The asynchronous read-signals strobe
when the lower 16-bits of the counter are read by software. The software can read the counter's high 16-bits
some time later after reading the lower 16-bits. The full 32-bit result reflects the timing of the first
asynchronous read strobe.
Totalize mode
The Totalize mode allows basic use of a 32-bit counter. While in this mode, the channel's input can only
increment the counter upward. When used as a 16-bit counter (counter low), one channel can be scanned at the
12 MHz rate. When used as a 32-bit counter (counter high), two sample times are used to return the full 32-bit
result. Therefore a 32-bit counter can only be sampled at a 6 MHz maximum rate. If you only want the upper 16
bits of a 32-bit counter, then you can acquire that upper word at the 12 MHz rate.
Figure 5. Typical PCI-2511 counter channel
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Functional Details