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Epson S1C17W15 Technical Manual page 94

Cmos 16-bit single chip microcontroller

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1/100-second
0
1
2
counter
3/256
2/256
3/256
s
s
s
1/10-second
0
counter
26/256 s
26/256 s
9.5 Interrupts
RTCA has a function to generate the interrupts shown in Table 9.5.1.
Interrupt
Alarm
RTCINTF.ALARMIF
1-day
RTCINTF.1DAYIF
1-hour
RTCINTF.1HURIF
1-minute
RTCINTF.1MINIF
1-second
RTCINTF.1SECIF
1/2-second
RTCINTF.1_2SECIF
1/4-second
RTCINTF.1_4SECIF
1/8-second
RTCINTF.1_8SECIF
1/32-second
RTCINTF.1_32SECIF See Figure 9.5.1.
Stopwatch 1 Hz
RTCINTF.SW1IF
Stopwatch 10 Hz
RTCINTF.SW10IF
Stopwatch 100 Hz
RTCINTF.SW100IF
Theoretical regulation
RTCINTF.RTCTRMIF At the end of theoretical regulation operation
completion
1 Hz counter
256 Hz
128 Hz
64 Hz
32 Hz
16 Hz
8 Hz
4 Hz
2 Hz
1 Hz
Interrupt flags
1/32-second interrupt
1/8-second interrupt
1/4-second interrupt
1/2-second interrupt
1-second interrupt
1-minute interrupt
1-hour interrupt
1-day interrupt
Notes: • 1-second to 1/32-second interrupts occur after a lapse of 1/256 second from change of the
1 Hz counter value.
• An alarm interrupt occurs after a lapse of 1/256 second from matching between the AM/PM (in
12H mode), hour, minute, and second counter value and the alarm setting value.
S1C17W15 TECHNICAL MANUAL
(Rev. 1.3)
25/256 seconds
3
4
5
6
7
2/256
3/256
2/256
3/256
2/256
s
s
s
s
s
1
2
3
25/256 s
25/256 s
26/256 × 6 + 25/256 × 4 = 1 second
Figure 9.4.4.1 Stopwatch Count-Up Patterns
Table 9.5.1 RTCA Interrupt Function
Interrupt flag
Matching between the RTCALM1–2 register contents
and the real-time clock counter contents
Day counter count up
Hour counter count up
Minute counter count up
Second counter count up
See Figure 9.5.1.
See Figure 9.5.1.
See Figure 9.5.1.
1/10-second counter overflow
1/10-second counter count up
1/100-second counter count up
Figure 9.5.1 RTCA Interrupt Timings
Seiko Epson Corporation
8
9
0
1
2
3/256
2/256
3/256
3/256
3/256
s
s
s
s
s
4
5
6
26/256 s
26/256 s
25/256 s
Set condition
9 REAL-TIME CLOCK (RTCA)
26/256 seconds
3
4
5
6
7
2/256
3/256
2/256
3/256
2/256
3/256
s
s
s
s
s
7
8
25/256 s
26/256 s
Clear condition
Writing 1
Writing 1
Writing 1
Writing 1
Writing 1
Writing 1
Writing 1
Writing 1
Writing 1
Writing 1
Writing 1
Writing 1
Writing 1
At counter count-up timing
8
9
2/256
s
s
9
26/256 s
9-5

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