Advertisement
17 LCD DRIVER (LCD8B)
17.7 Interrupt
The LCD8B has a function to generate the interrupt shown in Table 17.7.1.
Interrupt
Frame
LCD8INTF.FRMIF
The LCD8B provides an interrupt enable bit corresponding to the interrupt flag. An interrupt request is sent to the
interrupt controller only when the interrupt flag, of which interrupt has been enabled by the interrupt enable bit, is
set. For more information on interrupt control, refer to the "Interrupt Controller" chapter.
0
Frame signal
COM0
COMx
17.8 Control Registers
LCD8B Clock Control Register
Register name
Bit
LCD8CLK
15–9 –
8
7
6–4 CLKDIV[2:0]
3–2 –
1–0 CLKSRC[1:0]
Bits 15–9 Reserved
Bit 8
DBRUN
This bit sets whether the LCD8B operating clock is supplied in DEBUG mode or not.
1 (R/W): Clock supplied in DEBUG mode
0 (R/W): No clock supplied in DEBUG mode
Bit 7
Reserved
Bits 6–4
CLKDIV[2:0]
These bits select the division ratio of the LCD8B operating clock.
Bits 3–2
Reserved
Bits 1–0
CLKSRC[1:0]
These bits select the clock source of the LCD8B.
17-18
Table 17.7.1 LCD8B Interrupt Function
Interrupt flag
Frame switching
1 frame
x
Figure 17.7.1 Frame Interrupt Timings (1/x duty, 1/3 bias)
Bit name
Initial
0x00
DBRUN
1
–
0
0x0
0x0
0x0
Seiko Epson Corporation
Set condition
Writing 1
0
Reset
R/W
–
R
–
H0
R/W
–
R
H0
R/W
–
R
H0
R/W
Clear condition
x
V
(= V
C3
V
C2
V
C1
V
SS
V
(= V
C3
V
C2
V
C1
V
SS
Remarks
S1C17W15 TECHNICAL MANUAL
(Rev. 1.3)
)
C4
)
C4
Advertisement
