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T16BnCCCTLm.
CAPTRG[1:0] bits
(Trigger edge)
0x3 (↑ & ↓)
Rising or falling edge of the CAPnm pin input
signal
0x2 (↓)
Falling edge of the CAPnm pin input signal
0x1 (↑)
Rising edge of the CAPnm pin input signal
0x0
Bit 7
Reserved
Bit 6
TOUTMT
This bit selects whether the comparator MATCH signal of another system is used for generating the
TOUTnm signal or not.
1 (R/W): Generate TOUT using two comparator MATCH signals of the comparator circuit pair (0
and 1, 2 and 3, 4 and 5)
0 (R/W): Generate TOUT using one comparator MATCH signal of comparator m and the counter
MAX or ZERO signals
The T16BnCCCTLm.TOUTMT bit is control bit for comparator mode and is ineffective in capture
mode.
Bit 5
TOUTO
This bit sets the TOUTnm signal output level when software control mode (T16BnCCCTLm.TOUT-
MD[2:0] = 0x0) is selected for the TOUTnm output.
1 (R/W): High level output
0 (R/W): Low level output
The T16BnCCCTLm.TOUTO bit is control bit for comparator mode and is ineffective in capture
mode.
Bits 4–2
TOUTMD[2:0]
These bits configure how the TOUTnm signal waveform is changed by the comparator MATCH and
counter MAX/ZERO signals.
The T16BnCCCTLm.TOUTMD[2:0] bits are control bits for comparator mode and are ineffective in
capture mode.
T16BnCCCTLm.
TOUTMD[2:0]
T16BnCCCTLm.
bits
TOUTMT bit
Reset/set mode
0x7
0
1
Toggle/set mode
0x6
0
1
Reset mode
0x5
0
1
S1C17W15 TECHNICAL MANUAL
(Rev. 1.3)
Table 15.6.4 Trigger Signal/Edge for Capturing Counter Value
T16BnCCCTLm.CAPIS[1:0] bits (Trigger signal)
0x0 (External trigger signal)
Not triggered (disable capture function)
Table 15.6.5 TOUT Generation Mode
TOUT generation mode and operations
Count mode
Up count mode
TOUTnm
Up/down count mode
Down count mode
TOUTnm
All count modes
TOUTnm
TOUTnm+1 The signal becomes inactive by the MATCHm+1 signal and
Up count mode
TOUTnm
Up/down count mode
Down count mode
TOUTnm
All count modes
TOUTnm
TOUTnm+1 The signal is inverted by the MATCHm+1 signal and it be-
All count modes
TOUTnm
All count modes
TOUTnm
TOUTnm+1 The signal becomes inactive by the MATCHm+1 or
Seiko Epson Corporation
Trigger condition
0x2 (Software trigger signal = L) 0x3 (Software trigger signal = H)
Altering the T16BnCCCTLm.CAPIS[1:0] bits from 0x2 to 0x3, or
from 0x3 to 0x2
Altering the T16BnCCCTLm.CAPIS[1:0] bits from 0x3 to 0x2
Altering the T16BnCCCTLm.CAPIS[1:0] bits from 0x2 to 0x3
Output
Change in the signal
signal
The signal becomes inactive by the MATCH signal and it
becomes active by the MAX signal.
The signal becomes inactive by the MATCH signal and it
becomes active by the ZERO signal.
The signal becomes inactive by the MATCHm signal and it
becomes active by the MATCHm+1 signal.
it becomes active by the MATCHm signal.
The signal is inverted by the MATCH signal and it becomes
active by the MAX signal.
The signal is inverted by the MATCH signal and it becomes
active by the ZERO signal.
The signal is inverted by the MATCHm signal and it be-
comes active by the MATCHm+1 signal.
comes active by the MATCHm signal.
The signal becomes inactive by the MATCH signal.
The signal becomes inactive by the MATCHm or MATCHm+1
signal.
MATCHm signal.
15 16-BIT PWM TIMERS (T16B)
15-29
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