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8 WATCHDOG TIMER (WDT)
8.2.2 Clock Supply in DEBUG Mode
The CLK_WDT supply during DEBUG mode should be controlled using the WDTCLK.DBRUN bit.
The CLK_WDT supply to WDT is suspended when the CPU enters DEBUG mode if the WDTCLK.DBRUN bit = 0.
After the CPU returns to normal mode, the CLK_WDT supply resumes. Although WDT stops operating when the
CLK_WDT supply is suspended, the register retains the status before DEBUG mode was entered.
If the WDTCLK.DBRUN bit = 1, the CLK_WDT supply is not suspended and WDT will keep operating in DE-
BUG mode.
8.3 Operations
8.3.1 WDT Control
Starting up WDT
WDT should be initialized and started up with the procedure listed below.
1. Write 0x0096 to the MSCPROT.PROT[15:0] bits.
2. Configure the WDT operating clock.
3. Write 1 to the WDTCTL.WDTCNTRST bit.
4. Write a value other than 0xa to the WDTCTL.WDTRUN[3:0] bits.
5. Write a value other than 0x0096 to the MSCPROT.PROT[15:0] bits. (Set system protection)
Resetting WDT
WDT generates a system reset when the counter overflows. To avert system restart by WDT, its embedded
counter must be reset periodically via software while WDT is running.
1. Write 0x0096 to the MSCPROT.PROT[15:0] bits.
2. Write 1 to the WDTCTL.WDTCNTRST bit.
3. Write a value other than 0x0096 to the MSCPROT.PROT[15:0] bits. (Set system protection)
A location should be provided for periodically processing this routine. Process this routine within the t
cycle. After resetting, WDT starts counting with a new reset generation cycle.
If WDT is not reset within the t
8.3.2 Operations in HALT and SLEEP Modes
During HALT mode
WDT operates in HALT mode. HALT mode is therefore cleared by a reset if it continues for more than the reset gen-
eration cycle and the reset handler is executed. To disable WDT in HALT mode, stop WDT by writing 0xa to the
WDTCTL.WDTRUN[3:0] bits before executing the halt instruction. Reset WDT before resuming operations after
HALT mode is cleared.
During SLEEP mode
WDT operates in SLEEP mode if the selected clock source is running. In this case SLEEP mode is cleared by a reset if
it continues for more than the reset generation cycle and the reset handler is executed. Therefore, stop WDT by setting
the WDTCTL.WDTRUN[3:0] bits before executing the slp instruction.
If the clock source stops in SLEEP mode, WDT stops. To prevent generation of an unnecessary reset after clearing
SLEEP mode, reset WDT before executing the slp instruction. WDT should also be stopped as required using the
WDTCTL.WDTRUN[3:0] bits.
8-2
cycle for any reason, a system reset is generated.
WDT
Seiko Epson Corporation
(Remove system protection)
(Reset WDT counter)
(Start up WDT)
(Remove system protection)
(Reset WDT counter)
S1C17W15 TECHNICAL MANUAL
WDT
(Rev. 1.3)
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