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8.4 Control Registers
WDT Clock Control Register
Register name
Bit
WDTCLK
15–9 –
8
7–6 –
5–4 CLKDIV[1:0]
3–2 –
1–0 CLKSRC[1:0]
Bits 15–9 Reserved
Bit 8
DBRUN
This bit sets whether the WDT operating clock is supplied in DEBUG mode or not.
1 (R/WP): Clock supplied in DEBUG mode
0 (R/WP): No clock supplied in DEBUG mode
Bits 7–6
Reserved
Bits 5–4
CLKDIV[1:0]
These bits select the division ratio of the WDT operating clock (counter clock). The clock frequency
should be set to around 256 Hz.
Bits 3–2
Reserved
Bits 1–0
CLKSRC[1:0]
These bits select the clock source of WDT.
WDTCLK.
CLKDIV[1:0] bits
0x3
0x2
0x1
0x0
(Note) The oscillation circuits/external input that are not supported in this IC cannot be
selected as the clock source.
WDT Control Register
Register name
Bit
WDTCTL
15–8 –
7–5 –
4
3–0 WDTRUN[3:0]
Bits 15–5 Reserved
Bit 4
WDTCNTRST
This bit resets WDT.
1 (WP):
Reset
0 (WP):
Ignored
0 (R):
Always 0 when being read
S1C17W15 TECHNICAL MANUAL
(Rev. 1.3)
Bit name
Initial
0x00
DBRUN
0
0x0
0x0
0x0
0x0
Table 8.4.1 Clock Source and Division Ratio Settings
0x0
IOSC
1/16,384
1/8,192
1/4,096
1/2,048
Bit name
Initial
0x00
0x0
WDTCNTRST
0
0xa
Seiko Epson Corporation
Reset
R/W
–
R
–
H0
R/WP
–
R
H0
R/WP
–
R
H0
R/WP
WDTCLK.CLKSRC[1:0] bits
0x1
0x2
OSC1
OSC3
1/128
1/16,384
1/8,192
1/4,096
1/2,048
Reset
R/W
–
R
–
–
R
H0
WP
Always read as 0.
H0
R/WP –
8 WATCHDOG TIMER (WDT)
Remarks
0x3
EXOSC
1/1
Remarks
8-3
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