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16.3 Clock Settings
16.3.1 SNDA Operating Clock
When using SNDA, the SNDA operating clock CLK_SNDA must be supplied to SNDA from the clock generator.
The CLK_SNDA supply should be controlled as in the procedure shown below.
1. Enable the clock source in the clock generator if it is stopped (refer to "Clock Generator" in the "Power Supply,
Reset, and Clocks" chapter).
2. Set the following SNDCLK register bits:
- SNDCLK.CLKSRC[1:0] bits (Clock source selection)
- SNDCLK.CLKDIV[2:0] bits (Clock division ratio selection = Clock frequency setting)
The CLK_SNDA frequency should be set to around 32,768 Hz.
16.3.2 Clock Supply in SLEEP Mode
When using SNDA during SLEEP mode, the SNDA operating clock CLK_SNDA must be configured so that it will
keep supplying by writing 0 to the CLGOSC.xxxxSLPC bit for the CLK_SNDA clock source.
If the CLGOSC.xxxxSLPC bit for the CLK_SNDA clock source is 1, the CLK_SNDA clock source is deactivated
during SLEEP mode and SNDA stops with the register settings maintained at those before entering SLEEP mode.
After the CPU returns to normal mode, CLK_SNDA is supplied and the SNDA operation resumes.
16.3.3 Clock Supply in DEBUG Mode
The CLK_SNDA supply during DEBUG mode should be controlled using the SNDCLK.DBRUN bit.
The CLK_SNDA supply to SNDA is suspended when the CPU enters DEBUG mode if the SNDCLK.DBRUN
bit = 0. After the CPU returns to normal mode, the CLK_SNDA supply resumes. Although SNDA stops operating
when the CLK_SNDA supply is suspended, the output pin and registers retain the status before DEBUG mode was
entered. If the SNDCLK.DBRUN bit = 1, the CLK_SNDA supply is not suspended and SNDA will keep operating
in DEBUG mode.
16.4 Operations
16.4.1 Initialization
SNDA should be initialized with the procedure shown below.
1. Assign the SNDA output function to the ports. (Refer to the "I/O Ports" chapter.)
2. Configure the SNDA operating clock.
3. Set the SNDCTL.MODEN bit to 1.
4. Set the SNDSEL.SINV bit.
5. Set the following bits when using the interrupt:
- Write 1 to the interrupt flags in the SNDINTF register.
- Set the interrupt enable bits in the SNDINTE register to 1.
16.4.2 Buzzer Output in Normal Buzzer Mode
Normal buzzer mode generates a buzzer signal with the software specified frequency and duty ratio, and outputs
the generated signal to outside the IC. The buzzer output duration can also be controlled via software.
An output start/stop procedure and the SNDA operations are shown below.
Normal buzzer output start/stop procedure
1. Set the SNDSEL.MOSEL[1:0] bits to 0x0.
S1C17W15 TECHNICAL MANUAL
(Rev. 1.3)
Seiko Epson Corporation
16 SOUND GENERATOR (SNDA)
(Enable SNDA operations)
(Set output pin drive mode)
(Clear interrupt flags)
(Enable interrupts)
(Set normal buzzer mode)
16-3
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