J1 And J2 Signals - Kontron COMh-caRP User Manual

To protect external power lines of peripheral devices, make sure that the wires have the
right diameter to withstand the maximum available current. The enclosure of the
peripheral device fulfills the fire-protection requirements of IEC/EN 62368.

4.2 J1 and J2 signals

The type of an interface pin consists of the pin type and the buffer type.
Pin Types Description
I Input to the Module
O Output from the Module
I/O Bi-directional input / output signal
OD Open drain output
REF Analog reference voltage output – low voltage (GND min, 3.3V max)
Table 36: Pin Types
Buffer Types Description
Logic input or output. Input thresholds and output levels shall be at or over 80% of supply rail for the high side and at or
CMOS
under 20% of the relevant supply rail for the low side.
Low voltage differential signals – may include DP, TMDS, DP_AUX, MIPI D-PHY and HCSL (High Speed Current Steering Logic)
used for PCIe clock pairs.
LV_DIFF
Exact details for these variants differ, but the all of these signals are well under 3.3V and the LV_DIFF type label serves well
to describe them as a group.
KR Ethernet 25GBASE-KR or 10GBASE-KR compatible signal.
KX Ethernet 1000BASE-KX compatible signal.
DP Display Port compatible signal. Used for DDI interfaces.
MDI Media Dependent Interface, used for NBASE-T signaling.
NFET N channel FET output, drain pin, Module can pull low to GND or float.
PCIE PCI Express compatible differential signals. Includes signaling up to PCIe Gen 5.
PDS Pull-down strap. Module either pulls these lines to GND or leaves them open.
SATA SATA compatible differential signals.
USB USB 2.0 compliant differential signals.
USB_SS USB Super Speed compliant signals; includes USB 3.0, USB 3.1, USB 3.2 and USB4.
Table 37: Buffer Types
Other Notation Description
PD Pull-Down
PU Pull-Up
2K2 2.2 Kohm resistor (and so on for other values)
Table 38: Other Notation
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