St-Link/V2-1 Firmware Upgrade; Etm Trace; Table 4. Setting Of Configuration Elements For Trace Connector (Cn12) - ST STM32L476ZG User Manual

Hardware layout and configuration
6.1.2

ST-LINK/V2-1 firmware upgrade

For its operation, ST-LINK/V2-1 employs a dedicated MCU with flash memory. Its firmware
determines ST-LINK/V2-1 functionality and performance. The firmware might evolve during
the life span of STM32L476G-EVAL to include new functionality, fix bugs or support new
target microcontroller families. It is therefore recommended to keep ST-LINK/V2-1 firmware
up to date. The latest version is available from www.st.com.
6.2

ETM trace

The connector CN12 can output trace signals used for debugging. By default, the
Evaluation board is configured such that STM32L476ZG PE2 to PE5 signals are not
connected to trace outputs Trace_D0, Trace_D1, Trace_D2, Trace_D3, and Trace_CK of
CN12. They are used for other functions.
Table 4 shows the setting of configuration elements to shunt PE2, PE3, PE4, and PE5 MCU
ports to the CN12 connector, to use them as debug trace signals.

Table 4. Setting of configuration elements for trace connector (CN12)

Element
R103
SB26
R104
R84
SB40
R85
SB38
R86
SB39
Warning: Enabling the CN12 trace outputs through the hardware modifications described in
Table 4 results in reducing the memory address bus width to 19 address lines and so the
addressable space to 512 Kwords of 16 bits. As a consequence, the onboard SRAM and
NOR flash memory usable capacity is reduced to 8 Mbits.
16/80
Setting Use of PE2, PE3, PE4, PE5 terminals of STM32L476ZG
R103 in Default setting.
SB26 open PE2 connected to LCDSEG38 and memory address line A23.
R103 out
PE2 connected to TRACE_CK on CN12. A23 pulled down.
SB26 closed
Default setting.
R104 in
PE3 connected to LCDSEG39 and memory address line A19.
R104 out PE3 connected to TRACE_D0 on CN12. A19 pulled down.
R84 in Default setting.
SB40 open PE4 connected to memory address line A20.
R84 out
PE4 connected to TRACE_D1 on CN12. A20 pulled down.
SB40 closed
R85 in Default setting.
SB38 open PE5 connected to memory address line A21.
R85 out
PE5 connected to TRACE_D2 on CN12. A21 pulled down.
SB38 closed
R86 in Default setting.
SB39 open PE6 is used for address bit A22.
R86 out
PE6 connected to TRACE_D3 on CN12. A22 pulled down.
SB39 closed
UM1855 Rev 6
UM1855