Quad-Spi Flash Memory Device; Table 29. Configuration Elements Related To Quad-Spi Device - ST STM32L476ZG User Manual

UM1855
6.25

Quad-SPI flash memory device

A 256-Mbit Quad-SPI flash memory device is fitted on the STM32L476G-EVAL main board,
in the U9 position. It allows evaluating STM32L476ZG Quad-SPI flash memory device
interface.
This Quad-SPI flash memory can operate in single transfer rate (STR) and double transfer
rate (DTR) modes.
By default, the Quad-SPI flash memory device is not accessible.
configuration elements and their settings allowing to access the Quad-SPI flash memory
device. The LCD glass module daughterboard MB979 takes an active part in the
configuration. It must be removed from the main board (denoted as "MB979 out"), to operate
the Quad-SPI flash memory device.
information.
Element
SB12
SB13
MB979
SB14
SB15
MB979
SB18
SB19
MB979
SB21
SB20
MB979

Table 29. Configuration elements related to Quad-SPI device

Setting
Default setting.
SB12 open QSPI_D0 data line is not available at Quad-SPI flash memory device:
SB13 open PB1 port of STM32L476ZG is only routed to the MB979 daughterboard
connector (CN11).
SB12 closed QSPI_D0 data line is available at Quad-SPI flash memory device:
SB13 open PB1 port of STM32L476ZG is routed to the DQ0 port of the Quad-SPI
MB979 out flash memory device.
Default setting.
SB14 open QSPI_D1 data line is not available at Quad-SPI flash memory device:
SB15 open PB0 port of STM32L476ZG is only routed to the MB979 daughterboard
connector (CN11).
SB14 closed QSPI_D1 data line is available at Quad-SPI flash memory device:
SB15 open PB0 port of STM32L476ZG is routed to the DQ1 port of the Quad-SPI
MB979 out flash memory device.
Default setting.
SB18 open QSPI_D2 data line is not available at Quad-SPI flash memory device:
SB19 open PA7 port of STM32L476ZG is only routed to the MB979 daughterboard
connector (CN11).
SB18 closed QSPI_D2 data line is available at Quad-SPI flash memory device:
SB19 open PA7 port of STM32L476ZG is routed to the DQ2 port of the Quad-SPI
MB979 out flash memory device.
Default setting.
SB21 open QSPI_D3 data line is not available at Quad-SPI flash memory device:
SB20 open PA6 port of STM32L476ZG is only routed to the MB979 daughterboard
connector (CN11).
SB21 closed QSPI_D3 data line is available at Quad-SPI flash memory device:
SB20 open PA6 port of STM32L476ZG is routed to the DQ3 port of the Quad-SPI
MB979 out flash memory device.
UM1855 Rev 6
Hardware layout and configuration
Section 6.12: Motor control
Configuration
Table 29 shows the
provides additional
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