Display Timing Specifications - Advantech IDK-1115WP-45FHA2 User Manual

2.6

Display Timing Specifications

The input signal timing specifications are shown in the following table and timing dia-
gram.
Signal
LVDS Clock
Vertical Dis-
play Term
Horizontal Dis-
play Term
Note(1)! Because this module is operated by DE only mode, Hsync, and Vsync
input signals are ignored.
Note(2)! The Tv(Tvd+Tvb) must be integer, otherwise, this module would operate
abnormally.
IDK-1115WP-45FHA2 User Manual
Item Symbol Min.
Frequency Fc 60
Period Tc -
Input cycle to
Trcl -0.02*Tc
cycle jitter
Input clock to
TLVCCS -0.02*Tc
data skew
Spread spec-
Fclkin_
trum modula- FC*98%
mod
tion range
Spread spec-
trum modula-
FSSM -
tion
frequency
Frame Rate Fr 50
Total Tv 1090
Active Dis-
Tvd 1080
play
Blank Tvb Tv-Tvd
Total Th 1050
Active
Thd 960
Display
Blank Thb Th-Thd
Typ. Max.
70.93 75
14.1 -
- 0.02*Tc
- 0.02*Tc
- FC*102% MHz
- 200
60 60
1110 1130
1080 1080
30 Tv-Tvd
1065 1075
960 960
105 Th-Thd
12
Unit Note
MHz
ns
ns (3)
ns (4)
(5)
KHz
Hz Tv=Tvd+Tvb
Th
Th
Th
Tc Th=Thd+Thb
Tc
Tc