Input Signal Timing Specifications - Advantech IDK-1115R-40XGC2E User Manual

4.1

Input Signal Timing Specifications

The input signal timing specifications are shown as the following table and timing dia-
gram:
Signal Item
DCLK Pixel Clock
Vertical Total Time
Vertical Address Time
DE
Horizontal Total Time
Horizontal Address Time
Note Because this module is operated by DE only mode, Hsync and Vsync input sig-
nals should be set to low logic level or ground. Otherwise, this module will
operate abnormally.
IDK-1115R User Manual
Symbol Min. Typ.
1/T - 65
C
T 780 806
V
T 768 768
VD
T 1140 1344
H
T 1024 1024
HD
16
Max. Unit Note
80 MHz -
1200 T -
H
768 T -
H
1600 T -
C
1024 T -
C