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UG-040
R129
C125
R138
Figure 14. MCLK Loop Filter Selected
R129
C125
R138
Figure 15. LRCLK Loop Filter Selected
Normally, the MCLK filter is the default selection; it is also
possible to use the register control window to program the
PLL to run from the LRCLK. In this case, the jumper must
be changed as shown in Figure 15.
CONNECTING AUDIO CABLES
Analog Audio
The analog inputs and outputs use 3.5 mm TRS jacks; they are
configured in the standard configuration: tip = left, ring = right,
sleeve = ground. The analog inputs to IN1 and IN2 generate
0 dBFS from a 1 V rms analog signal. The on-board buffer
circuit creates the differential signal to drive the ADC with
2 V rms at the maximum level. The DAC puts out a 1.8 V rms
differential signal; this signal becomes single-ended for the OUT
connectors. There are test points that allow direct access to the
ADC and DAC pins; note that the ADC and DAC have a
common-mode voltage of 1.5 V dc. These test points require
proper care so that improper loading does not drag down the
common-mode voltage, and the headroom and performance of
the part do not suffer.
The ADC buffer circuit is designed with a switch (S1) that
allows the user to change the voltage reference for all of the
amplifiers. GND, CM, and FILTR can be selected as a reference;
it is advisable to shut down the power to the board before
changing this switch. The CM and FILTR lines are very
sensitive and do not react well to a change in load while the
AD1937/AD1939 is active. A series of jumpers allows the user
to dc-couple the buffer circuit to the ADC analog port when
CM and FILTR are selected (see Figure 16).
PLL SELECT
C120
JP15
C131
PLL SELECT
C120
JP15
C131
R72
C60
IN1L
U12
TP25
C69
R84
R86
C76
TP30
IN1R
U14
C99
R106
Figure 16. VREF Selection and DC Coupling Jumpers
Digital Audio
There are two types of digital interfacing, S/PDIF and discrete
serial. The input and output S/PDIF ports have both optical and
coaxial connectors. The serial audio connectors use 1 × 2 100 mil
spaced headers with pins for both signal and ground. The
LRCLK, BCLK, and SDATA paths are available for both the
ADC and DAC on the HDR1 and HDR2 connectors. Each has a
connection for MCLK; each HDR MCLK interface has a switch
to set the port as an input or output, depending on the master
or slave state of the AD1937/AD1939.
SWITCH AND JUMPER SETTINGS
Clock and Control
The AD1937/AD1939 are designed to run in standalone mode
at a sample rate (f
(256 × f
). In standalone slave mode, both ADC and DAC ports
S
must receive valid BCLK and LRCLK. The AD1937/AD1939
can be clocked from either the S/PDIF receiver or the HDR1
connector; the ADC BCLK and LRCK port sources are selected
with SW2, Position 2 and Position 3. For S/PDIF master, both
switches should be off. For HDR1, SW2, Position 3, should be
on (see the detail in Figure 17 and Figure 18). The DAC BCLK
and LRCK port sources are selected with SW2, Position 5 and
Position 6. For S/PDIF master, both switches should be off. For
HDR1, SW2, Position 6, should be on. Note that HDR2 is not
implemented in the CPLD routing code.
It is also possible to configure the AD1937/AD1939 ADC
BCLK and LRCK ports to run in standalone master mode;
moving J5 to SDA/1, as shown in Figure 3, changes the state of
the AD1937/AD1939. Setting SW2, Position 2 and Position 5, to
on selects the proper routing to both the S/PDIF receiver and
the HDR1 connector. In this mode, the AD1937/AD1939 ADC
port generates BCLK and LRCLK when given a valid MCLK.
Rev. 0 | Page 6 of 32
Evaluation Board User Guide
R73
C63
C61
TP26
C65
IN1L+
C64
IN1L–
C67
TP28
R85
R87
C80
C77
TP32
C83
IN1R+
C82
IN1R–
C88
TP34
R107
) of 48 kHz, with an MCLK of 12.288 MHz
S
S1
C74
VREF SELECT
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