Evaluation Board User Guide
193X_MCLKI
DISABLE
JP18
JP19
1938_MCLKI
JP22
R160
L7
C158
JP23
CPLD
U21
JP25
HDR2
JP27
OSC DISABLE
HDR1
JP28
EXT
CLK
JP29
8416
JP30
HDR2
JP31
HDR1
Figure 10. External Clock In as Master; the AD1939 and CPLD as Slaves
193X_MCLKI
DISABLE
JP18
JP19
1938_MCLKI
JP22
R160
L7
C158
JP23
CPLD
U21
JP25
HDR2
JP27
OSC DISABLE
HDR1
JP28
EXT
CLK
JP29
8416
JP30
HDR2
JP31
HDR1
Figure 11. Active On-Board Oscillator as Master; the AD1939 and
CPLD as Slaves
The MCLK configurations shown in Figure 12 and Figure 13
use the
AD1937/AD1939
MCLKO port to drive the CPLD and,
possibly, the HDRs. The passive crystal runs the AD1937/AD1939
at 12.288 MHz. Figure 13 shows the MCLKI shut off; this is the
case when the PLL is set to lock to LRCLK instead of to MCLK.
JP20
C147
MCLKO
XTAL
U18
Y1
193X_MCLKO
R167
R169
R172
U22
R174
R175
C168
EXT CLK IN
C170
JP20
C147
MCLKO
XTAL
U18
Y1
193X_MCLKO
R167
R169
R172
U22
R174
R175
C168
EXT CLK IN
C170
J22
1938_MCLKI
L7
C158
J23
OSC DISABLE
Figure 12. Passive Crystal; the AD1939 Is Master and the CPLD Is Slave from
J22
1938_MCLKI
L7
C158
J23
OSC DISABLE
Figure 13. LRCLK Is the Master Clock Using the PLL; MCLKI Is Disabled, and
CONFIGURING THE PLL FILTER
The PLL for the AD1937/AD1939 can run from either MCLK
or LRCLK, according to its setting in the PLL and Clock Control 0
register, Bits[6:5]. The matching RC loop filter must be con-
nected to LF (Pin 61) using JP15. See Figure 14 and Figure 15
for the jumper positions.
Rev. 0 | Page 5 of 32
193X_MCLKI
DISABLE
JP20
JP18
MCLKO
XTAL
JP19
JP22
R160
Y1
JP23
CPLD
R167
U21
JP25
HDR2
R169
JP27
R172
HDR1
U22
JP28
EXT
CLK
R174
JP29
8416
C168
C170
JP30
HDR2
JP31
HDR1
the MCLKO Port
193X_MCLKI
DISABLE
JP20
JP18
MCLKO
XTAL
JP19
JP22
R160
Y1
JP23
CPLD
R167
U21
JP25
HDR2
R169
JP27
R172
HDR1
U22
JP28
EXT
CLK
R174
JP29
8416
C168
C170
JP30
HDR2
JP31
HDR1
CPLD Is Slave to the MCLKO Port
UG-040
C147
J22
U18
193X_MCLKO
J23
R175
EXT CLK IN
C147
J22
U18
193X_MCLKO
J23
R175
EXT CLK IN
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