Table of Contents
Advertisement
KTD-N0876-0
and IRDY# are sampled asserted. During a read, TRDY# indicates that valid
data is present on AD[31::00]. During a write, it indicates the target is
prepared to accept data. Wait cycles are inserted until both IRDY# and
TRDY# are asserted together.
Stop indicates the current target is requesting the master to stop the
STOP#
current transaction.
Lock indicates an atomic operation that may require multiple transactions
LOCK#
to complete. When LOCK# is asserted, non-exclusive transactions may proceed
to an address that is not currently locked. A grant to start a transaction
on PCI does not guarantee control of LOCK#. Control of LOCK# is obtained
under
its
different agents to use PCI while a single master retains ownership of
LOCK#. If a device implements Executable Memory, it should also implement
LOCK# and guarantee complete access exclusion in that memory. A target of
an access that supports LOCK# must provide exclusion to a minimum of 16
bytes (aligned). Host bridges that have system memory behind them should
implement LOCK# as a target from the PCI bus point of view and optionally
as a master.
Initialization Device Select is used as a chip select during configuration
IDSEL
read and write transactions.
Device Select, when actively driven, indicates the driving device has
DEVSEL#
decoded its address as the target of the current access. As an input,
DEVSEL# indicates whether any device on the bus has been selected.
ARBITRATION PINS (BUS MASTERS ONLY)
Request indicates to the arbiter that this agent desires use of the bus.
REQ#
This is a point to point signal. Every master has its own REQ# which must
be tri-stated while RST# is asserted.
Grant indicates to the agent that access to the bus has been granted. This
GNT#
is a point to point signal. Every master has its own GNT# which must be
ignored while RST# is asserted.
While RST# is asserted, the arbiter must ignore all REQ# lines since they
are tri-stated and do not contain a valid request. The arbiter can only
perform arbitration after RST# is deasserted. A master must ignore its GNT#
while RST# is asserted. REQ# and GNT# are tri-state signals due to power
sequencing requirements when 3.3V or 5.0V only add-in boards are used with
add-in boards that use a universal I/O buffer.
ERROR REPORTING PINS.
The error reporting pins are required by all devices and maybe asserted when enabled
Parity Error is only for the reporting of data parity errors during all PCI
PERR#
transactions except a Special Cycle. The PERR# pin is sustained tri-state
and must be driven active by the agent receiving data two clocks following
the data when a data parity error is detected. The minimum duration of
PERR# is one clock
detected. (If sequential data phases each have a data parity error, the
PERR# signal will be asserted for more than a single clock.) PERR# must be
driven high for one clock before being tri-stated as with all sustained
tri-state signals. There are no special conditions when a data parity error
may be lost or when reporting of an error may be delayed. An agent cannot
report a PERR# until it has claimed the access by asserting DEVSEL# (for a
target)
and
transaction.
System Error is for reporting address parity errors, data parity errors on
SERR#
the Special Cycle command, or any other system error where the result will
be catastrophic. If an agent does not want a non-maskable interrupt (NMI)
to be generated, a different reporting mechanism is required. SERR# is pure
open drain and is actively driven for a single PCI clock by the agent
reporting the error. The assertion of SERR# is synchronous to the clock and
meets the setup and hold times of all bused signals. However, the restoring
of SERR# to the deasserted state is accomplished by a weak pullup (same
value as used for s/t/s) which is provided by the system designer and not
by the 55signaling agent or central resource. This pull-up may take two to
three clock periods to fully restore SERR#. The agent that reports SERR#s
Page 55
own
protocol
in
conjunction
for each data phase
completed
a
data
KTA75/Flex Users Guide
KTA75/Flex Users Guide
Connector Signal Definition
with
GNT#.
Slot Connectors
that a data parity
phase
or
is
the
master
It
is
possible
for
error is
of
the
current
Advertisement
Table of Contents
