4-6.4.3 Cpu & Pci Bus Control - SOLTEK SL-85ERV4-R Manual

SL-85ERV4-R/85ERV4-RL
4-6.4.3 CPU & PCI Bus Control
Choose "CPU & PCI Bus Control" in "Advanced Chipset Features" and
press <Enter>. The following sub-screen will appear for CPU & PCI
Bus Control configuration:
PCI Master 0 WS Write
VLink mode selection
VLink 8X Support
PCI Master 0 WS Write When Enabled, writing to the PCI bus are executed
VLink mode selection Allows you select VLink mode.
VLink 8X Support Default is enabled to improve the system
Memory Hole In order to improve performance, certain space in
System BIOS
Cacheable
Init Display First Initialize the AGP video display before initializing any
CPU & PCI Bus Control
with zero wait states.
Choices: Enabled, Disabled
Choices: By Auto; Mode 0; Mode 1; Mode 2; Mode
3; Mode 4
performance.
○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
memory is reserved for ISA cards. This memory must
be mapped into the memory space below 16MB.
The choices: 15M-16M; Disabled
Selecting Enabled allows caching of the system
BIOS ROM at F0000h-FFFFFh, resulting in better
system performance.
other display device on the system. Thus the AGP
display becomes the primary display.
Enabled
By Auto
Enabled
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Chapter 4 BIOS Setup
Item Help
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