SOLTEK SL-85ERV4-R Manual page 54

SL-85ERV4-R/85ERV4-RL
DRAM Clock This item allows you to set the DRAM Clock.
DRAM Timing This item allows you to set the DRAM Timing.
SDRAM CAS Latency With SDRAM Timing by SPD disabled, you can se-
Bank Interleave This value appears when "DRAM Timing" is set at
Precharge to Active
Active to Precharge
Active to CMD(Trcd) This value appears when "DRAM Timing" is set at
REF to ACT/REF to
REF(Trfc)
ACT(0) to ACT (1)
DRAM Command Rate Allows you to set the DRAM Command Rate.
Delay Dclk Control Allows you to enable / disable the Delay Dclk Control.
SPD (Serial Presence Detect) is located on the
memory modules, BIOS reads information coded in
SPD during system boot up.
Choices: By SPD; 100MHz;133MHz; 166MHz;
200MHz
Choices: Auto By SPD; Manual
lect the SDRAM CAS# (Column Address Strode)la-
tency manually. Choices: 1.5; 2.0; 2.5; 3.0
"Manual". Choices: 2 Bank; 4 Bank; Disabled
This value appears when "DRAM Timing" is set at
(Trp) "Manual". Choices: 2T; 3T; 4T; 5T
This value appears when "DRAM Timing" is set at
(Tras) "Manual". Choices: 6T; 7T; 8T; 9T
"Manual". Choices: 2T; 3T; 4T; 5T
This value appears when "DRAM Timing" is set at
"Manual". Choices: 12T; 13T; 14T; 15T
This value appears when "DRAM Timing" is set at
"Manual". Choices: 2T; 3T
(TRRD)
Choices: 1T Command; 2T Command
57
Chapter 4 BIOS Setup