Alinx ARTIX-7FPGA User Manual page 38

The 2 channel Gigabit Ethernet pin assignments are as follows：
nd
Signal Name
E2_GTXC
E2_TXD0
E2_TXD1
E2_TXD2
E2_TXD3
E2_TXD4
E2_TXD5
E2_TXD6
E2_TXD7
E2_TXEN
E2_TXER
E2_TXC
E2_RXC
E2_RXDV
E2_RXER
E2_RXD0
E2_RXD1
E2_RXD2
E2_RXD3
E2_RXD4
E2_RXD5
E2_RXD6
E2_RXD7
E2_COL
E2_CRS
E2_RESET
E2_MDC
E2_MDIO
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ARTIX-7 FPGA Development Board AX7201 User Manual
FPGA Pin
M16
L15
K16
W15
W16
V17
W17
U15
V15
M15
T15
T14
J20
L13
G13
M13
K14
K13
J14
H14
H15
J15
H13
J11
E22
L14
AB21
AB22
Description
Ethernet GMII transmit clock
Ethernet Transmit Data bit0
Ethernet Transmit Data bit1
Ethernet Transmit Data bit2
Ethernet Transmit Data bit3
Ethernet Transmit Data bit4
Ethernet Transmit Data bit5
Ethernet Transmit Data bit6
Ethernet Transmit Data bit7
Ethernet transmit enable signal
Ethernet sends an error signal
Ethernet GMII transmit clock
Ethernet GMII receive clock
Ethernet receive data valid signal
Ethernet receiving data error
Ethernet Receive Data Bit0
Ethernet Receive Data Bit1
Ethernet Receive Data Bit2
Ethernet Receive Data Bit3
Ethernet Receive Data Bit4
Ethernet Receive Data Bit5
Ethernet Receive Data Bit6
Ethernet Receive Data Bit7
Ethernet Collision signal
Ethernet Carrier Sense Signal
Ethernet Reset Signal
Ethernet Management Clock
Ethernet Management Data
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