Alinx ARTIX-7FPGA User Manual page 37

The 1 channel Gigabit Ethernet pin assignments are as follows：
st
Signal Name
E1_GTXC
E1_TXD0
E1_TXD1
E1_TXD2
E1_TXD3
E1_TXD4
E1_TXD5
E1_TXD6
E1_TXD7
E1_TXEN
E1_TXER
E1_TXC
E1_RXC
E1_RXDV
E1_RXER
E1_RXD0
E1_RXD1
E1_RXD2
E1_RXD3
E1_RXD4
E1_RXD5
E1_RXD6
E1_RXD7
E1_COL
E1_CRS
E1_RESET
E1_MDC
E1_MDIO
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ARTIX-7 FPGA Development Board AX7201 User Manual
FPGA Pin
G21
D22
H20
H22
J22
K22
L19
K19
L20
G22
K17
K21
K18
M22
N18
N22
H18
H17
M21
L21
N20
M20
N19
M18
L18
G20
J17
L16
Description
Ethernet GMII transmit clock
Ethernet Transmit Data bit0
Ethernet Transmit Data bit1
Ethernet Transmit Data bit2
Ethernet Transmit Data bit3
Ethernet Transmit Data bit4
Ethernet Transmit Data bit5
Ethernet Transmit Data bit6
Ethernet Transmit Data bit7
Ethernet transmit enable signal
Ethernet transmit error signal
Ethernet GMII transmit clock
Ethernet GMII receive clock
Ethernet receive data valid signal
Ethernet receiving data error
Ethernet Receive Data Bit0
Ethernet Receive Data Bit1
Ethernet Receive Data Bit2
Ethernet Receive Data Bit3
Ethernet Receive Data Bit4
Ethernet Receive Data Bit5
Ethernet Receive Data Bit6
Ethernet Receive Data Bit7
Ethernet Collision signal
Ethernet Carrier Sense Signal
Ethernet Reset Signal
Ethernet Management Clock
Ethernet Management Data
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