Using The Board Test System; The System Info Tab; Board Information; Jtag Chain - Altera Cyclone V SoC User Manual

Chapter 6: Board Test System

Using the Board Test System

A GUI appears, displaying the application tab that corresponds to the design running
in the FPGA. The Cyclone V development board's flash memory ships preconfigured
with the design that corresponds to the GPIO tab.
1
Under two conditions, the BTS displays a message prompting you to configure your
board with a valid BTS design:
If you power up your board with the DIP switch (SW2.3) in a position other than
■
the on (0) position
■ If you load your own design into the FPGA with the Quartus II Programmer
Using the Board Test System
This section describes each control in the BTS.

The System Info Tab

The System Info tab shows board's current configuration.
shows the System Info tab. The tab displays the contents of the MAX V registers, the
JTAG chain, the board's MAC address, the flash memory map, and other details
stored on the board.
The following sections describe the controls on the System Info tab.

Board Information

The Board information controls display static information about your board.
Board Name—Indicates the official name of the board.
■
■ Part number—Indicates the part number of the board.
■ Serial number—Indicates the serial number of the board.
■ Factory test version—Indicates the version of the Board Test System currently
running on the board.
MAC1—Indicates the MAC address of the board's ENET1 10/100 port.
■
■ MAC2—Indicates the MAC address of the board's ENET2 10/100 port.
■ HPS MAC1—Indicates the MAC address of the board's HPS 10/100/1000
Ethernet port.
■ MAX V ver—Indicates the version of MAX V code currently running on the
board. The MAX V code resides in the <install
dir>\kits\cycloneVSX_5csxfc6df31es_soc\examples directory. Newer revisions
of this code might be available on the
Altera website.

JTAG Chain

The JTAG chain control shows all the devices currently in the JTAG chain. The
Cyclone V device is always the first device in the chain. The JTAG chain is normally
mastered by the On-board USB-Blaster II.
May 2013 Altera Corporation
Figure 6–1 on page 6–1
Cyclone V SoC Development Kit
Cyclone V SoC Development Kit
6–3
page of the
User Guide