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2.12 Watch-Dog Timer
There are three access cycles of Watch-Dog Timer as Enable,
Refresh and Disable. The Enable cycle should proceed by READ
PORT 443H. The Disable cycle should proceed by READ PORT
045H. A continue Enable cycle after a first Enable cycle means
Refresh.
Once if the Enable cycle activity, a Refresh cycle is request before
the time-out period for restart counting the WDT Timer's period.
Otherwise, it will assume that the program operation is abnormal
when the time counting over the period preset of WDT Timer. A
System Reset signal to start again or a NMI cycle to the CPU comes
if over.
The JP14 is using for select the active function of watch-dog timer in
disable the watch-dog timer, or presetting the watch-dog timer
activity at the reset trigger, or presetting the watch-dog timer activity
at the NMI trigger.
JP14 : Watch-Dog Active Type Setting
JP14
*2-3
1-2
OFF
JP10 ( pin 5-6, 7-8, 9-10 ) : WDT Time - Out Period
PERIOD
*1 sec
2 sec
10 sec
20 sec
110 sec
220 sec
DESCRIPTION
System Reset
Active NMI
disable Watch-dog timer
WD2
WD1
5 – 6
7 – 8
ON
ON
OFF
ON
ON
OFF
OFF
OFF
ON
ON
OFF
ON
WD0
9 – 10
ON
ON
ON
ON
OFF
OFF
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