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2.13 Watch-Dog Timer

There are three access cycles of Watch-Dog Timer as Enable,
Refresh and Disable. The Enable cycle should proceed by READ
PORT 443H. The Disable cycle should proceed by READ PORT
043H. A continue Enable cycle after a first Enable cycle means
Refresh.
Once if the Enable cycle activity, a Refresh cycle is request before
the time-out period for restart counting the WDT Timer's period.
Otherwise, it will assume that the program operation is abnormal
when the time counting over the period preset of WDT Timer. A
System Reset signal to start again or a NMI cycle to the CPU comes
if over.
The JP8 is using for select the active function of watch-dog timer in
disable the watch-dog timer, or presetting the watch-dog timer
activity at the reset trigger, or presetting the watch-dog timer activity
at the NMI trigger.
JP8 : Watch-Dog Active Type Setting
l
JP8
*1-2
2-3
OFF
JP4 : WDT Time - Out Period
l
PERIOD
*1 sec
2 sec
10 sec
20 sec
110 sec
220 sec
16
disable Watch-dog timer
1-2
3-4
OFF
OFF
OFF
OFF
OFF
ON
OFF
ON
ON
OFF
ON
OFF
DESCRIPTION
System Reset
Active NMI
5-6
ON
ON
OFF
OFF
OFF
OFF
7-8
OFF
ON
OFF
ON
OFF
ON

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