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Inputs
Input signals
W
Internal pull-up resistor 1 k
Trigger by making contact against 0 V or
by low-level signal over TTL logic device
£
Delay for set/zero reset: t
d
Minimum pulse duration for all signals: t
Signal level of inputs
Status
Level
High
+ 3.9 V
Low
– 0.5 V
E
0V
E
0V
, active with low level
2 ms
³
30 ms
min
£
£
U
+ 15 V
£
£
£
U
+ 0.9 V; I
6 mA
³ÿ
t
30 ms
min
t
min
Outputs
Output signals
"Open collector" outputs, active with low level
£
Delay until signal output: t
d
Signal duration of zero signal, trigger limit A1, A2: t
Signal level of outputs
Status
High
Low
C
B
U CE
E
Pin 1.10
30 ms
³
180 ms
0
Level
£
£
U
+ 32 V; I
10 µA
£
£
U
+ 0.4 V; I
100 mA
I ≤ 100 mA
+ U B ≤ 32 V
0 V
39
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