Evaluation Board Overview; Motherboard - Analog Devices EVAL-ADP5020 Manual

EVALUATION BOARD OVERVIEW

MOTHERBOARD

INT/EXT SUPPLIES
JUMPER SELECTION
VBATT LED
INDICATOR
VDDIO LED
INDICATOR
VBOARD LED
INDICATOR
SYNC PIN
SELECTION
EXTERNAL
FREQUENCY
ON SYNC PIN
CONNECTOR
The ADP5020 motherboard provides the interface signals to the
ADP5020 power management IC. These include the SDA and
2
SCL lines for I C, or the control line voltages for the hardware
interface modes (EN/GPIO, SYNC, and XSHTDWN).
The Cypress Semiconductor Corporation CY7C68013A
provides the USB interface and I
frequency is 100 kHz. The M24C64R serial EEPROM provides
the USB address of the board. The interface voltage is selected
with the VBOARD header on the board and is set to 3.3 V by
default.
Typically, the daughterboard is inserted directly into the 2 × 20-pin
header of the motherboard. For temperature measurements,
however, it may be necessary to use an extension cable to connect
the motherboard and the daughterboard because the Cypress
CY7C68013A is not rated at −40°C. The 8-pin Header J10 on
the top of the motherboard can be used to connect external
supplies.
The VBATT OKAY, VDDIO OKAY, and VBOARD OKAY LEDs
located at the top left of the board lights up when the board is
powered from the USB cable, or when external supplies are
connected to J10 and Jumper LK8 to Jumper LK10 are set in the
EXTERNAL
SUPPLIES
DAUGHTERBOARD
CONNECTORS
Figure 23. Motherboard
2 2
C signals. The selected I C
Rev. 0 | Page 13 of 24
USB
CONNECTOR
EXT position. It is possible to choose several supply combinations.
For example, VBOARD, which supplies the motherboard ICs, can
be provided from the USB while VDDIO and VBATT are provided
externally. The motherboard contains three LDOs generating
the default supply voltage, as indicated in Table 1.
Table 1. Power Supply Options
Supply Line
VBATT
VDDIO
VBOARD
Jumper LK11 defines the forcing level for the EN/GPIO pin.
With the jumper in the low position, the EN/GPIO pin is forced
to logic low. With the jumper in the high position, the EN/GPIO
pin is forced to logic high. The VDDIO supply line determines
the logic level.
Jumper LK12 selects the clock mode for the SYNC pin. With the
jumper in the GND position, the SYNC pin is tied to ground. With
the jumper in the EXT position, an external frequency can be
applied to the SYNC pin through Connector SM2. The logic level
of the clock signal must be referred to the VDDIO supply level.
EVAL-ADP5020
EN PIN EXTERNAL
FORCING LEVEL
EN/GPIO
STATUS LED
BUCK2 REGULATOR
ACTIVATION LED
LDO REGULATOR
ACTIVATION LED
BUCK1 REGULATOR
ACTIVATION LED
XSHTDWN
STATUS LED
ADP5020 TEST-POINTS
LK8 to LK10 in LK8 to LK10 in EXT
USB Position Position
Internal: 3.7 V External: 2.3 V to 5.5 V
Internal: 2.0 V External: 1.7 V to 3.6 V
Internal: 3.3 V External: 2.7 V to 3.6 V